Application Note 1822
AN1822.1
May 7, 2015
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9
Efficiency Curves
Input = 12VDC, Output = 5V/20A, 3.3V/20A.
FIGURE 14. EFFICIENCY vs OUTPUT POWER
FIGURE 15. POWER LOSS vs OUTPUT POWER
FIGURE 16. OUTPUT LOAD REGULATION 5V
FIGURE 17. OUTPUT LOAD REGULATION 3.3V
90
91
92
93
94
95
96
97
0
20
40
60
80
100
120
140
160
180
LOAD POWER (W)
E
F
F
ICIENCY (%
)
FULL LOAD 5V/20A, 3.3V/20A
0
1
2
3
4
5
6
7
8
9
10
11
12
0
20
40
60
80
100
120
140
160
180
LOAD POWER (W)
PO
WER
LO
SS
(W)
FULL LOAD 5V/20A, 3.3V/20A
4.96
4.97
4.98
4.99
5.00
5.01
5.02
5.03
5.04
0
2
4
6
8
10
12
14
16
18
20
22
OUTPUT CURRENT (A)
O
U
TPU
T
V
OL
TAGE
(
V
)
3.30
3.31
3.32
3.33
3.34
3.35
3.36
0
2
4
6
8
10
12
14
16
18
20
22
OUTPUT CURRENT (A)
OU
TPU
T
V
OL
TAGE
(
V
)
Steady State Operation
1st stage LC (2µH + 2*47µF) + 2nd stage LC Output Filters (200nH + 820µF).
FIGURE 18. GATE DRIVER AND SWITCHING TRANSIENT
FIGURE 19. GATE DRIVER AND SWITCHING TRANSIENT
PHASE
LGATE
NO LOAD, HIGH-SIDE MOS TURNS OFF
LOW-SIDE MOS TURNS ON
THERE IS ENOUGH DEAD TIME
20A LOAD, HIGH-SIDE MOS TURNS OFF
LOW-SIDE MOS TURNS ON
PHASE
LGATE
