2
AN1291.0
May 17, 2007
Test Set-up
FIGURE 1. TEST SET-UP
Switch Descriptions
• S1: Channel-1 Enable
- OFF: Short the Channel-1 EN pin to GND (disable
PWM)
- ON: Allow the Channel-1 EN pin to pull-up to +5V
(enable PWM)
• S4: Channel-1 Dynamic Load
- OFF: On-board Channel-1 dynamic load disabled
- ON: On-board Channel-1 dynamic load enabled
• S5: Channel-1 V
O
Increase
- OFF: V
O1
is 1.5V, determined by R
15
and R
23
.
- ON: Parallel R
49
with R
15
. V
O1
is 1.8V.
• S2: Channel-2 Enable
- OFF: Short the Channel-2 EN pin to GND (disable
PWM)
- ON: Allow the Channel-2 EN pin to pull-up to +5V
(enable PWM)
• S3: Channel-2 Dynamic Load
- OFF: On-board Channel-2 dynamic load disabled
- ON: On-board Channel-2 dynamic load enabled
Test-point Descriptions
• J4: Scope-probe socket for measuring PHASE1
• J6: Scope-probe socket for measuring V
O1
• J12: Scope-probe socket for measuring the current of the
Channel-1 on-board transient-load emulator
• J3: Scope-probe socket for measuring the PHASE2 node
• J5: Scope-probe socket for measuring V
O2
• J11: Scope-probe socket for measuring the current of the
Channel-2 on-board transient-load emulator
• TP1: Monitor the 5V positive input
• TP2: Monitor the 5V return input
• TP3: Monitor the PGOOD2 pin
• TP4: Monitor the PGOOD1 pin
• TP5: The common node of R
24
and R
20
; Useful for
Channel-1 loop gain measurement.
• TP6: The common node of R
25
and R
23
; Useful for
Channel-2 loop gain measurement
• TP7: The V
O1
side of R
24
; Useful for Channel-1 loop gain
measurement.
• TP8: The V
O2
side of R
25
; Useful for Channel-1 loop gain
measurement.
• TP9: Monitor the V
IN1
positive input
• TP10: Monitor the V
IN1
return input
• TP11: Monitor the positive V
O1
output
• TP12: Monitor the V
O1
return output
• TP13: Monitor the positive V
O2
output
• TP14: Monitor the V
O2
return output
• TP15: Monitor the 12V positive input
• TP16: Monitor the 12V return input
• TP17: Monitor the EN1 pin
• TP18: Monitor the gate of transistor Q
18
• TP19: Monitor the EN2 pin
• TP20: Monitor the V
IN2
positive input
• TP21: Monitor the V
IN2
return input
S2
J1
J2
J9
J10
ISL6228EVAL3Z
ON
OFF
TP11
+
_
5V
+
_
V
O1
+
_
V
O2
READING
J14
J13
TP1
TP2
V
IN1
V
IN2
_
+
S3
S1
S4
S5
ON
OFF
ON
OFF
ON
OFF
VO1 INCREASE
J7
J8
V
O2
_
+
TP12
TP14
TP13
J4
J3
J5
J6
V
+
_
V
O1
READING
V
+
_
J12
J11
TP15
TP16
12V
+
_
Application Note 1291
Содержание ISL6228EVAL3Z
Страница 10: ...10 AN1291 0 May 17 2007 FIGURE 15 LAYER 1 ISL6228EVAL3Z Evaluation Board Layout Continued Application Note 1291...
Страница 11: ...11 AN1291 0 May 17 2007 FIGURE 16 LAYER 2 ISL6228EVAL3Z Evaluation Board Layout Continued Application Note 1291...
Страница 12: ...12 AN1291 0 May 17 2007 FIGURE 17 LAYER 3 ISL6228EVAL3Z Evaluation Board Layout Continued Application Note 1291...