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3-22

Interrupt Servicing

Register R(1) is always used as the program counter when-
ever interrupt servicing is initiated. When an interrupt
request occurs and the interrupt is allowed by the program
(again, nothing takes place until the completion of the cur-
rent instruction), the contents of the X and P registers are
stored in the temporary register T, and X and P are set to
new values; hex digit 2 in X and hex digit 1 in P. Interrupt
Enable is automatically deactivated to inhibit further inter-
rupts. The user's interrupt routine is now in control; the con-
tents of T may be saved by means of a single instruction (78)
in the memory location pointed to by R(X). At the conclusion
of the interrupt, the user's routine may restore the pre-inter-
rupted value of X and P with a single instruction (70 or 71).
The Interrupt Enable flip-flop can be activated to permit fur-
ther interrupts or can be disabled to prevent them.

CPU Register Summary

CDP1802 Control Modes

The WAIT and CLEAR lines provide four control modes as
listed in the following truth table:

The function of the modes are defined as follows:

Load

Holds the CPU in the IDLE execution state and allows an I/O
device to load the memory without the need for a “bootstrap”
loader. It modifies the IDLE condition so that DMA-lN opera-
tion does not force execution of the next instruction.

Reset

Registers l, N, Q are reset, lE is set and 0’s (VSS) are placed on
the data bus. TPA and TPB are suppressed while reset is held
and the CPU is placed in S1. The first machine cycle after ter-
mination of reset is an initialization cycle which requires 9 clock
pulses. During this cycle the CPU remains in S1 and register X,
P, and R(0) are reset. Interrupt and DMA servicing are sup-

pressed during the initialization cycle. The next cycle is an S0,
S1, or an S2 but never an S3. With the use of a 71 instruction
followed by 00 at memory locations 0000 and 0001, this feature
may be used to reset IE, so as to preclude interrupts until ready
for them. Power-up reset can be realized by connecting an RC
network directly to the CLEAR pin, since it has a Schmitt trig-
gered input, see Figure 24.

Pause

Stops the internal CPU timing generator on the first negative
high-to-low transition of the input clock. The oscillator contin-
ues to operate, but subsequent clock transitions are ignored.

Run

May be initiated from the Pause or Reset mode functions. If
initiated from Pause, the CPU resumes operation on the first
negative high-to-low transition of the input clock. When initi-
ated from the Reset operation, the first machine cycle follow-
ing Reset is always the initialization cycle. The initialization
cycle is then followed by a DMA (S2) cycle or fetch (S0) from
location 0000 in memory.

Run-Mode State Transitions

The CPU state transitions when in the RUN and RESET
modes are shown in Figure 25. Each machine cycle requires
the same period of time, 8 clock pulses, except the initializa-
tion cycle, which requires 9 clock pulses. The execution of
an instruction requires either two or three machine cycles,
S0 followed by a single S1 cycle or two S1 cycles. S2 is the
response to a DMA request and S3 is the interrupt response.
Table 2 shows the conditions on Data Bus and Memory
Address lines during all machine states.

Instruction Set

The CPU instruction summary is given in Table 1. Hexadeci-
mal notation is used to refer to the 4-bit binary codes.

In all registers bits are numbered from the least significant bit
(LSB) to the most significant bit (MSB) starting with 0.

R(W): Register designated by W, where

W = N or X, or P

R(W).0: Lower order byte of R(W)

R(W).1: Higher order byte of R(W)

Operation Notation

M(R(N))

→

D; R(N) + 1

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