
IRDC3046
6
Rev. 1.0
05/22/02
www.irf.com
Figure 4 -
Ch1: Gate signal for control FET (master, pin-15).
Ch2: Gate signal for control FET (slave, pin-10).
Ch3: Inductor current for master channel (L3).
Ch4: Inductor current for slave channel (L4).
V
MASTER
=5V, V
SLAVE
=12V, I
OUT
=10A
Figure 5 -
Ch1: Gate signal for sync FET (master, pin-14).
Ch2: Gate signal for sync FET (slave, pin-11).
Ch3: Inductor current for master channel (L3).
Ch4: Inductor current for slave channel (L4).
V
MASTER
=5V, V
SLAVE
=12V, I
OUT
=10A
Figure 6 -
Ch1: Gate signal for control FET (master, pin-15).
Ch2: Gate signal for sync FET (master, pin-14).
Ch3: Gate signal for control FET (slave, pin-10).
Ch4: Gate signal for sync FET (slave, pin-11).
TEST DATA