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TAHOE 8724 User Guide
Rev: 01
8/10/2017
Page 25 OF 45
Interface Masters Technologies Inc. Confidential & Proprietary
2.2.2
Power Sequencing Control
CPLD enables over time the various voltage regulators to meet the voltage
Turn-On requirements for various IC. During this process, it checks the various Power-
Good indication signals before enabling the next voltages in the sequence.
2.2.3
Access Interface
The CN78XX’s Boot Bus is the main interface to access the internal registers of the
CPLD and utilizes SPI interface from a debug header. The pinout of the header matches
the pinout for the Altera Byte Blaster.