Errata
Specification Update
29
AZ20.
EFLAGS, CR0, CR4 and the EXF4 Signal May Be Incorrect after Shutdown
Problem:
When the processor is going into shutdown due to an RSM inconsistency failure, EFLAGS,
CR0 and CR4 may be incorrect. In addition the EXF4 signal may still be asserted. This
may be observed if the processor is taken out of shutdown by NMI#.
Implication:
A processor that has been taken out of shutdown may have an incorrect EFLAGS, CR0
and CR4. In addition the EXF4 signal may still be asserted.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AZ21.
Premature Execution of a Load Operation Prior to Exception Handler
Invocation
Problem:
If any of the below circumstances occur, it is possible that the load portion of the
instruction will have executed before the exception handler is entered:
If an instruction that performs a memory load causes a code segment limit violation.
If a waiting X87 floating-point (FP) instruction or MMX™ technology (MMX)
instruction that performs a memory load has a floating-point exception pending.
If an MMX or SSE/SSE2/SSE3/SSSE3 extensions (SSE) instruction that performs a
memory load and has either CR0.EM=1 (Emulation bit set), or a floating-point Top-
of-Stack (FP TOS) not equal to 0, or a DNA exception pending.
Implication:
In normal code execution where the target of the load operation is to write back memory
there is no impact from the load being prematurely executed, or from the restart and
subsequent re-execution of that instruction by the exception handler. If the target of the
load is to uncached memory that has a system side-effect, restarting the instruction may
cause unexpected system behavior due to the repetition of the side-effect. Particularly,
while CR0.TS [bit 3] is set, a MOVD/MOVQ with MMX/XMM register operands may issue a
memory load before getting the DNA exception.
Workaround:
Code which performs loads from memory that has side-effects can effectively
workaround this behavior by using simple integer-based load instructions when accessing
side-effect memory and by ensuring that all code is written such that a code segment
limit violation cannot occur as a part of reading from side-effect memory.
Status:
For the steppings affected, see the Summary Tables of Changes.
