Intel® Server Boards SE7320SP2 and SE7525GP2
Functional Architecture
Revision 4.0
55
3.8 Clock Generation and Distribution
All buses on the server board operate using synchronous clocks. Clock synthesizer/driver
circuitry on the server board generates clock frequencies and voltage levels as required,
including the following:
200 MHz differential Clock at 0.7 V logic levels. For Processor 0, Processor 1, Debug
Port and MCH.
100 MHz differential Clock at 0.7 V logic levels on CK409B. For DB800 clock buffer.
100 MHz differential Clock at 0.7 V logic levels on DB800. For PCI Express* Device is
MCH. And for SATA is Intel
®
6300ESB.
66 MHz at 3.3 V logic levels: For MCH and Intel 6300ESB
48 MHz at 3.3V logic levels: For Intel 6300ESB and SIO.
33 MHz at 3.3V logic levels: For Intel 6300ESB, Video, BMC and SIO.
14.318 MHz at 2.5 V logic levels: For Intel 6300ESB and video.
10 MHz at 5V logic levels: For mini BMC.
3.8.1
Real Time Clock
The real time clock is specified to operate within the following criteria and environmental
conditions:
RTC accuracy: 1 minute per month = 2 seconds per day
Environmental conditions:
-
Temperature: 10 ~ 35 C
-
Humidity: 20 ~80% (non-condensing)
Содержание SE7320SP2 - 800MHZ Ecc Ddr Xeon
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