Functional Architecture Overview
Intel® Server Board S2600CO Family TPS
30
Revision
1.4
Intel order number G42278-004
system. However, since each channel is a Sparing Domain, the correctable error counting
continues for other channels which are still in a redundant state. There can be as many SFO
Events as there are memory channels with DIMMs installed.
3.2.2.5.6
Mirrored Channel Mode
Channel Mirroring Mode gives the best memory RAS capability by maintaining two copies of the
data in main memory. If there is an Uncorrectable ECC error, the channel with the error is
disabled and the system continues with the “good” channel, but in a non-redundant
configuration.
For Mirroring mode to be available as a RAS option, the DIMM population must be identical
between each pair of memory channels that participate. Not all channel pairs need to have
memory installed, but for each pair, the configuration must match. If the configuration is not
matched up properly, the memory operating mode falls back to Independent Channel Mode.
Mirroring Mode is enabled/disabled in the Memory RAS and Performance Configuration screen
in the <F2> BIOS Setup Utility.
When Mirroring Mode is operational, each channel in a pair is “mirrored” by the other channel.
The impact on Effective Memory size is to reduce by half the total amount of installed memory
available for use. When Mirroring Mode is operational, the system treats Correctable Errors the
same way as it would in Independent channel mode. There is a correctable error threshold.
Correctable error counts accumulate by rank, and the first event is logged.
What Mirroring primarily protects against is the possibility of an Uncorrectable ECC Error
occurring with critical data “in process”. Without Mirroring, the system would be expected to
“Blue Screen” and halt, possibly with serious impact to operation. But with Mirroring Mode in
operation, an Uncorrectable ECC Error from one channel becomes a Mirroring Fail Over (MFO)
event instead, in which the IMC retrieves the correct data from the “mirror image” channel and
disables the failed channel. Since the ECC Error was corrected in the process of the MFO Event,
the ECC Error is demoted to a Correctable ECC Error. The channel pair becomes a single non-
redundant channel, but without impacting operations, and the Mirroring Fail Over Event is
logged to SEL to alert the user that there is memory hardware that has failed and needs to be
replaced.
3.2.3
Processor Integrated I/O Module (IIO)
The processor’s integrated I/O module provides features traditionally supported through chipset
components. The integrated I/O module provides the following features:
PCI Express* Interfaces
: The integrated I/O module incorporates the PCI Express*
interface and supports up to 40 lanes of PCI Express*. Following are key attributes of
the PCI Express* interface:
o
Gen3 speeds up to 8 GT/s
o
X16 interface bifurcated down to two x8 or four x4 (or combinations)
o
X8 interface bifurcated down to two x4
DMI2 Interface to the PCH
: The platform requires an interface to the legacy
Southbridge (PCH) which provides basic, legacy functions required for the server
platform and operating systems. Since only one PCH is required and allowed for the
system, any sockets which do not connect to PCH would use this port as a standard x4
PCI Express* 2.0 interface.
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