68
Intel
®
PXA27x Processor Developer’s Kit
- User’s Guide
3.2.2.12
FPGA Revision ID (REVID)
Register REVID contains the revision number of the FPGA code resident this particular board.
These are listed in
4
Sx_RESET
R/W
Card reset signal:
0 = Card reset is deasserted.
1 = Card reset is asserted.
3:0
Sx_PWR
R/W
MAX1602 power-supply control signals:
PWR[3] = A1VCC
PWR[2] = A0VCC
PWR[1] = A1VPP
PWR[0] = A0VPP
NOTE:
See the MAX1602 data sheet for more information.
†
Reset values depend on the states of the corresponding signals.
Table 30. PCMCIA0/1 Bit Definitions (Sheet 2 of 2)
Physical Address:
0x0800_00E0
0x0800_00E4
PCMCIA0 (x = socket = 0)
PCMCIA1 (x = socket = 1)
Intel
®
PXA27x Processor Developer’s Kit
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
reserved
Sx_nIR
Q
Sx_n
S
P
K
R
_
BVD2
S
x
_
n
STSCHG
_
BVD1
Sx_nVS
Sx_n
CD
Sx_RESET
Sx_PWR
Reset
?
?
?
?
?
†
†
†
†
†
†
1
0
0
0
0
Bits
Name
Access
Description
Table 31. FPGA Bit Definitions
Physical Address: 0x0800_00F0
REVID
Intel
®
PXA27x Processor Developer’s Kit
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
RevID.X
RevID.Y
RevID.Z
Reset
†
†
†
†
†
†
†
†
†
†
†
†
†
†
†
†
Bits
Name
Access
Description
15:0
REVID
R
Revision ID of the FPGA (X.YZ)
†
Value determined by Revision of the FPGA Code resident.