Intel Pentium III Processor/840, Руководство пользователя, Страница: 29 / 151

Intel
®
Pentium
®
III Processor/840 Development Kit Manual 3-5
Theory of Operation
3.3.3.3 Firmware Hub (FWH)
Firmware Hub (FWH) stores system BIOS and video BIOS, as well as an Intel Random Number
Generator (RNG). The Intel RNG provides truly random numbers to enable stronger encryption,
digital signing and security protocols. The FWH is key to enabling future security and
manageability infrastructures for the applied computing platform.
3.3.3.4 The 64-bit PCI Controller Hub (P64H)
The 64-bit PCI Controller Hub (P64H) supports 64-bit PCI slots at speeds of either 33 or 66 MHz.
The P64H connects directly to the MCH using Intel Accelerated Hub Architecture, providing a
dedicated path for high performance I/O. The Intel 82806AA PCI-64 Hub (P64H) is a multi-
function PCI device that provides a PCI bridging function and an I/O Advanced Peripheral
Interrupt Controller (APIC) function. The P64H is an integral part of the Intel 840 chipset and has
been implemented in this evaluation board design.
3.3.3.5 RDRAM-based Memory Repeater Hub (MRH-R)
For systems needing high RDRAM capacity, an RDRAM-based memory repeater hub
(MRH-R) may be utilized. The MRH-R converts each memory channel into two memory channels
for expanded memory capacity. MRH-R has not been implemented in this evaluation board.
3.3.3.6 SDRAM-based Memory Repeater Hub (MRH-S)
For systems needing high SDRAM capacity, an SDRAM-based memory repeater hub
(MRH-S) may be utilized. The MRH-S efficiently translates the RDRAM protocol into SDRAM-
based signals for system memory flexibility. The Pentium
III processor/840 Development Kit does
not provide support for SDRAM and the MRH-S has not been implemented on the evaluation
board.
3.3.4 System Memory RDRAM
The MCH on the evaluation board provides support for RDRAM.
Memory features include:
•
Up to 1 Gbyte with 128-Mbit technology
•
Up to 2 Gbyte with 256-Mbit technology
•
Dual Lock Step Direct RDRAM channel
•
Maximum 32 RDRAM-D devices per channel
•
SPD driven configuration of the 840 chipset for optimal memory operation
•
Support for ECC single- and multiple-bit detection (single- or double-bit correction), using
ECC RIMMs (ECC can be disabled via BIOS set-up).
•
Empty RIMM slots require a continuity RIMM card, (C-RIMM).
Both banks of memory must have identical configurations. A slot in bank 0 must have the same
size RIMM as the corresponding slot in bank 1. This is due to the lockstep feature, which means
the MCH reads and writes data to each bank simultaneously.