Intel NetStructure ZT 5085, Руководство пользователя

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Technical Product Specification
Specifications
A.6.2 Peripheral Slot P1/P2 Interfaces
This section defines the P1/P2 interface for peripheral slots.
A.6.2.1 Peripheral Slot P1 Interface
Table 21 specifies the P1 interface for the peripheral slots. The interface is in accordance with the
PICMG* 2.0 R3.0 and PICMG 2.16 R1.0 specifications. Refer to the PICMG specifications for
more detail. Exceptions are noted below the table.
Table 21. CompactPCI* Peripheral Slot P1 Pin Assignments
Pin # Z A B C D E F
25 GND 5 V REQ64# ENUM# 3.3 V 5 V GND
24 GND AD[1] 5 V V(I/O) AD[0] ACK64# GND
23 GND 3.3 V AD[4] AD[3] 5 V AD[2] GND
22 GND AD[7] GND 3.3 V AD[6] AD[5] GND
21 GND 3.3 V AD[9] AD[8] M66EN C/BE[0]# GND
20 GND AD[12] GND V(I/O) AD[11] AD[10] GND
19 GND 3.3 V AD[15] AD[14] GND AD[13] GND
18 GND SERR# GND 3.3 V PAR C/BE[1]# GND
17 GND 3.3 V IPMB_SCL IPMB_SDA GND PERR# GND
16 GND DEVSEL# GND V(I/O) STOP# LOCK# GND
15 GND 3.3 V FRAME# IRDY# BD_SEL# TRDY# GND
14 GND (KEY) (KEY) (KEY) (KEY) (KEY) GND
13 GND (KEY) (KEY) (KEY) (KEY) (KEY) GND
12 GND (KEY) (KEY) (KEY) (KEY) (KEY) GND
11 GND AD[18] AD[17] AD[16] GND C/BE[2]# GND
10 GND AD[21] GND 3.3 V AD[20] AD[19] GND
9 GND C/BE[3]# IDSEL AD[23] GND AD[22] GND
8 GND AD[26] GND V(I/O) AD[25] AD[24] GND
7 GND AD[30] AD[29] AD[28] GND AD[27] GND
6 GND REQ# 3.3 V CLK AD[31] GND
5 GND BRSVP1A5 BRSVP1B5 PCI_RST# GND GNT# GND
4 GND IPMB_PWR HEALTHY# V(I/O) INTP INTS GND
3 GND INTA# INTB# INTC# 5 V INTD# GND
2 GND TCK
†
5 V TMS TDO TDI
†
GND
1 GND 5 V -12 V TRST# +12 V 5 V GND
NOTES:
† The JTAG signals (TCK, TMS, TDO, and TDI) are not routed on the backplane.The JTAG signals (TCK,
TMS, TDO, and TDI) are not routed on the backplane.e JTAG signalsThe JTAG signals (TCK, TMS, TDO,
and TDI) are not routed on the backplane.The JTAG signals (TCK, TMS, TDO, and TDI) are not routed on
the backplane.The JTAG signals (TCK, TMS, TDO, and TDI) are not routed on the backplane.