Intel IXP45X, Руководство разработчика

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Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors—Expansion Bus
Controller
Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
Developer’s Manual August 2006
682 Order Number: 306262-004US
and 8-word aligned read transfers for 8-word burst lengths. The Expansion bus
controller also supports write data transfers for byte, halfword (half-word aligned), 1-
word (word aligned), and 8-word (8-word aligned) burst lengths. The Expansion bus
controller determines the burst size based upon EX_BURST and EX_BE_N and a list of
supported transfer types are shown in Table 223 . For writes EX_ADDR[1:0] is always
ignored, since EX_BE_N indicates which bytes need to be written. For 8-word writes the
Expansion bus controller ignores EX_BE_N. For reads EX_ADDR[1:0] and EX_BE_N are
ignored since the Expansion bus controller does not perform sub-word reads. The
Expansion bus controller will have unpredictable results if the external master
generates an unsupported data transfer. For 8-word reads and writes, the external
master must drive EX_ADDR[4:2] to 0x0 on the first address cycle of the burst. Also
EX_ADDR[24:5] must not change during an 8-word burst. For 8-word writes, the burst
ends when EX_ADDR[4:2] = 0x7. For writes, EX_ADDR[4:2] is increment by 0x1 after
each word is transferred. Reads do not require all 8 words to be transferred. EX_DATA
always lags EX_ADDR by one cycle for reads and writes.
Read transactions start with EX_SLAVE_CS_N and EX_RD_N asserted. The cycle after
EX_SLAVE_CS_N is asserted, the Expansion bus controller will always assert
EX_WAIT_N since it has to obtain the read data from the AHB bus. For read data
transfers, the Expansion bus controller starts to drive EX_DATA (with invalid data) two
cycles after the assertion of EX_SLAVE_CS_N. After the Expansion bus controller
receives the data from the AHB bus, it deasserts EX_WAIT_N and drives EX_DATA with
valid data. A state machine showing the Expansion bus inbound states is shown in
Figure 148 . The Expansion bus controller will never assert EX_WAIT_N again after
deasserting EX_WAIT_N, unless a new transfer is started.
As soon as the master samples EX_WAIT_N deasserted it can end the transfer for 1-
word read by deasserting EX_SLAVE_CS_N. The master can then leave
EX_SLAVE_CS_N deasserted for any length of cycles and start a new transaction by
asserting EX_SLAVE_CS_N. Alternatively, as soon as the master samples EX_WAIT_N
deasserted the master can start a new read transfer by never deasserting
Table 223. Supported Inbound Expansion Bus Transfers
Expansion Bus
Cycle
EX_BURST EX_BE_N
AHB Address
Value
(AHB_ADDR[1:0]
)
AHB_HSIZE AHB_HBURST
Data Translation
between EX_DATA
and AHB_DATA
(EXP_BYTE_SWAP_
EN = 0)
Byte write 0 0xE 11 byte single
EX_DATA[7:0] =
AHB_DATA[7:0]
Byte write 0 0xD 10 byte single
EX_DATA[15:8] =
AHB_DATA[15:8]
Byte write 0 0xB 01 byte single
EX_DATA[23:16] =
AHB_DATA[23:16]
Byte write 0 0x7 00 byte single
EX_DATA[31:24] =
AHB_DATA[31:24]
Halfword write 0 0xC 10 halfword single
EX_DATA[15:0] =
AHB_DATA[15:0]
Halfword write 0 0x3 00 halfword single
EX_DATA[31:16] =
AHB_DATA[31:16]
1-word write 0 0x0 00 word single
EX_DATA[31:0] =
AHB_DATA[31:0]
8-word write 1 X 00 word incr8
EX_DATA[31:0] =
AHB_DATA[31:0]
1-word read 0 X 00 word single
EX_DATA[31:0] =
AHB_DATA[31:0]
8-word read 1 X 00 word incr8
EX_DATA[31:0] =
AHB_DATA[31:0]