Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Руководство пользователя, Страница: 83 / 1898

1:72 Volume 1, Part 1: Application Programming Model
The following instructions are defined for flush control: flush cache (
fc
,
fc.i
) and flush
write buffers (
fwb
). The
fc
instruction invalidates the cache line in all levels of the
memory hierarchy above memory. If the cache line is not consistent with memory, then
it is copied into memory before invalidation. The
fc.i
instruction ensures the data
cache line associated with an address is coherent with the instruction caches. The
fc.i
instruction is not required to invalidate the targeted cache line nor write the targeted
cache line back to memory if it is inconsistent with memory, but may do so if this is
required to make the targeted cache line coherent with the instruction caches. The
fwb
instruction provides a hint to flush all pending buffered writes to memory (no indication
of completion occurs).
Table 4-19 summarizes the memory hierarchy control instructions and hint
mechanisms.
4.4.6.2 Memory Consistency
In the Itanium architecture, instruction accesses made by a processor are not coherent
with respect to instruction and/or data accesses made by any other processor, nor are
instruction accesses made by a processor coherent with respect to data accesses made
by that same processor. Therefore, hardware is not required to keep a processor’s
instruction caches consistent with respect to any processor’s data caches, including that
processor’s own data caches; nor is hardware required to keep a processor’s instruction
caches consistent with respect to any other processor’s instruction caches. Data
accesses from different processors in the same coherence domain are coherent with
respect to each other; this consistency is provided by the hardware. Data accesses
from the same processor are subject to data dependency rules; see
“Memory Access
Ordering” below.
The mechanism(s) by which coherence is maintained is implementation dependent.
Separate or unified structures for caching data and instructions are not architecturally
visible. Within this context there are two categories of data memory hierarchy control:
allocation and flush. Allocation refers to movement towards the processor in the
hierarchy (lower numbered levels) and flush refers to movement away from the
processor in the hierarchy (higher numbered levels). Allocation and flush occur in
line-sized units; the minimum architecturally visible line size is 32 bytes (aligned on a
32-byte boundary). The line size in an implementation may be smaller in which case
the implementation will need to move multiple lines for each allocation and flush event.
An implementation may allocate and flush in units larger than 32 bytes.
In order to guarantee that a write from a given processor becomes visible to the
instruction stream of that same, and other, processors, the affected line(s) must be
made coherent with instruction caches. Software may use the
fc.i
instruction for this
Table 4-19. Memory Hierarchy Control Instructions and Hint Mechanisms
Mnemonic Operation
.nt1 and. nta completer on loads Load usage hints
.nta
completer on stores Store usage hints
Prefetch line at post-increment address on loads and stores Prefetch hint
lfetch, lfetch.fault
with
.nt1
,.
nt2
, and
.nta
hints Prefetch line
fc, fc.i Flush cache
fwb Flush write buffers