Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Руководство пользователя

Страница: 800 / 1898

2:552 Volume 2, Part 2: Context Management
In principal, preserved GRs and FRs need not be spilled/filled when entering the kernel.
Whatever function is called from the low-level interruption handler or the system call
entry point will itself observe the calling conventions and preserve the registers. The
only occasion when preserved registers need to be spilled/filled is on a process or
thread context switch. However, many operating systems provide
get_context()
functions that provide user context upon demand. Although such functions are called
infrequently, many operating systems prefer to pay the penalty of spilling preserved
registers at system call and at interruption entry points to avoid the complexity of
piecing together user state from various potentially unknown kernel stack locations on
demand. Fortunately, the amount of preserved Itanium general register state is
relatively small, and the Itanium architecture provides additional mechanisms for lazy
floating-point state management. See
Section 4.2.2 for details.
Stacked GRs are managed by the register stack engine (RSE). On process/thread
context switches the operating system is required to completely flush the register stack
to its backing store in memory (using the
flushrs
instruction). In cases where the
operating system knows that it will return to the user process along the same path, e.g.
in system calls and exception handling code, the Itanium architecture allows operating
systems to switch the register stack backing store without having to flush all stacked
registers to memory. This allows such kernel entry points to switch from the user’s to
the kernel’s backing store without causing any memory traffic, as described in the next
section.
4.2.1 Preservation of Stacked Registers in the OS
A switch from a thread of execution into the operating system kernel, whether on
behalf of an involuntary interruption or a voluntary system call, requires preservation of
the stacked registers. Instead of flushing all dirty stacked register’s to memory, the RSE
can be used to automatically preserve the stacked registers of the interrupted context.
Table 4-2. Register State Preservation at Different Points in the OS
Register Type
Number of
Registers
System Call
(Voluntary)
Lightweight
Interrup-
tions
a
(Involuntary)
a. For details on lightweight interruption handlers refer to Section 3.4.1, “Lightweight Interruptions” on
page 2:543 .
Heavyweight
Interrup-
tions
b
(Involuntary)
b. For details on heavyweight interruption handlers refer to Section 3.4.2, “Heavyweight Interruptions” on
page 2:544 .
Process/Thread
Context Switch
(Voluntary)
Scratch GRs 23 no spill/fill
required
Untouched
(use banked
registers)
spill/fill
required
no spill/fill required
(done at interruption)
Preserved GRs 4 no spill/fill
required
Untouched
(use banked
registers)
no spill/fill
required
spill/fill
required
Stacked GRs 96 Backing Store
Switch
Untouched Backing Store
Switch
Synchronous
Backing Store Switch
using flushrs
c
c. Refer to Section 6.11.3, “Synchronous Backing Store Switch” for details.
Scratch FRs 106 no spill/fill
required
Untouched spill/fill
required
no spill/fill required
(done at interruption)
Preserved FRs 20 no spill/fill
required
Untouched no spill/fill
required
spill/fill
required