Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Руководство пользователя, Страница: 801 / 1898

Volume 2, Part 2: Context Management 2:553
Automatic preservation offers performance benefits: the register stack may contain
only a handful of dirty registers, system call parameters can be passed on the register
stack, and, upon return to the interrupted context the
loadrs
instruction only needs to
restore registers that were actually spilled to memory. Since system call rates scale
with processor performance, the RSE offers a key method for reducing the kernel’s
execution time of a system call.
To ensure operating system integrity the RSE requires a valid backing store (i.e. one
with a valid page mapping). The validity of the current backing store depends on the
interrupted context. If the interrupted context is itself a kernel thread, then its backing
store is in a known state, and no backing store switch is required (assuming that kernel
interruptions are nested). If the interrupted context is a user process, then the backing
store could be pointing at an invalid region of memory, and software is required to
redirect the RSE at a kernel backing store.
Section 6.11.1, “Switch from Interrupted
Context” on page 2:148 describes the code sequence to switch the RSE backing store
without causing memory traffic.
If the kernel redirects the backing store to a kernel memory region, then the kernel
must restore the backing store of the interrupted context prior to resumption of the
interrupted context. The kernel must also restore the register stack to its interrupted
state by manually pulling the spilled registers from the backing store. The kernel uses
the
loadrs
instruction to restore stacked registers from the backing store. The
loadrs
instruction requires the backing store pointer to align with any registers spilled from the
interrupted context. Thus the kernel should have paired all function calls (
br.call
instructions) with function returns (
br.ret
instructions), or manually manipulated the
kernel backing store pointer, so that all kernel contents have been removed from the
kernel backing store prior to the
loadrs
. After loading the stacked registers, the kernel
can switch to the backing store of the interrupted frame. This code sequence is
described in
Section 6.11.1, “Switch from Interrupted Context” on page 2:148 .
The kernel may occasionally gather the complete interrupted user context, such as to
satisfy a debugger request or to provide extended information to a user signal handler.
To provide the preserved register stack contents, including NaT values, the kernel must
extract the user context values from its backing store.
4.2.2 Preservation of Floating-point State in the OS
A full preservation of Itanium floating-point register file requires approximately 2
KBytes of memory. To reduce the frequency of such large register spills and fills, the
Itanium architecture offers additional mechanisms for lazy floating-point state
management. These features allow the system programmer to eliminate many
unnecessary floating-point state spills and fills especially around voluntary and
involuntary entries into the kernel, e.g. around system calls, external interrupts and
exceptions. Lazy state preservation can provide a significant reduction of memory
traffic and hence faster interrupt handlers and system calls, especially since most
interrupt handlers and much system code rarely perform floating-point computations.
The 126 non-constant floating-point registers are architecturally divided into the lower
set (FR2-31) and the higher set (FR32-127). The Itanium architecture provides two
floating-point register set “modified” bits, PSR.mfl and PSR.mfh, which are set by
hardware upon a write to any register in the lower and higher sets, respectively. The
“modified” bits are accessible to a user process through the user mask. Additionally,