Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Руководство пользователя

Страница: 780 / 1898

2:532 Volume 2, Part 2: MP Coherence and Synchronization
• Programmed I/O for paging of code pages.
• DMA for paging of code pages.
The next four sections discuss these techniques in greater depth.
To illustrate the code sequences for self- and cross-modifying code, the examples in
this section use the syntax “
st [foo] = new
” to represent a group of aligned stores that
change the instruction at address
foo
to the instruction “
new
”. The Itanium architecture
requires that the instruction stream see aligned stores atomically. In addition, the
syntax “
fc.i foo
” represents a group of flush cache instructions that ensures the cache
line addressed by
foo
is coherent with all the instruction caches. Updating more than
one instruction simply requires the appropriate store/flush “pair” for each updated
instruction
1
.
2.5.1 Self-modifying Code
Figure 2-8 presents the Itanium instruction sequence necessary to update a code
image location on the local processor only.
This code fragment changes the instruction at the address
code
to the new instruction
new_inst
. After executing this code, the change is visible to both the local processor’s
caches and its pipeline.
The
st
instruction updates the code image and the
fc.i
instruction ensures the value
stored is coherent with the instruction cache. The
fc.i
is necessary because the
Itanium architecture does not require instruction caches to be coherent with data stores
for Itanium architecture-based code. Next, the
sync.i
ensures that the code update is
visible to the instruction stream of the local processor and orders the cache flush with
respect to subsequent operations by waiting for the prior
fc.i
instructions to be made
visible. Finally, the
srlz.i
instruction forces the pipeline to re-initiate any instruction
group fetches it performed after the
srlz.i
and also waits for the
sync.i
to complete;
effectively making the pipeline coherent with the updated code image.
The serialization instruction is not necessary if software can guarantee that the
processor encounters an event that re-initiates code fetches performed after the
sync.i
, such as an interruption or an
rfi
, before executing the new code. Events such
as an interrupt or
rfi
both perform an instruction serialization which in this example
waits for the
sync.i
to complete and then re-initiates code fetches.
1. This description hides some of the complexity involved. Specifically, the flush and store operations
have different sizes. Whereas multiple store instructions are necessary to update a 16 byte instruc-
tion, a single cache line flush invalidates at least two 16 byte instructions.
Figure 2-8. Updating a Code Image on the Local Processor
patch_local:
st [code] = new_inst // write new instruction
fc.i code ;; // flush new instruction
sync.i ;; // sync i stream with store
srlz.i ;; // serialize
// Local caches and pipeline are now coherent with new_inst...