Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Руководство пользователя

Страница: 763 / 1898

Volume 2, Part 2: MP Coherence and Synchronization 2:515
This contradicts the postulated outcome r1 = 0 and r2 = 0 and thus the Itanium
memory ordering model disallows the r1 = 1 and r2 = 0 outcome. Specifically, if M3
reads 0, then M4, M5, and M6 may not yet be visible but M1 and M2 must be visible.
Thus, when M6 becomes visible it must observe x = 1 because M1 is already visible.
2.2.1.6 Data Dependency Does Not Establish MP Ordering
The dependency rules define the relationship between memory operations that access
the same address. Specifically, the Itanium architecture resolves read-after-write
(RAW), write-after-read (WAR), and write-after-write (WAW) dependencies through
memory in program order on the local processor. As
Section 2.2 discusses,
dependencies are fundamentally different from the ordering semantics even though
both affect ordering relationships between groups of memory accesses.
The execution shown in Table 2-5 illustrates this difference.
The following discussion focuses on the outcome r1 = 1, r2 = 1, and r3 = 0. This
outcome is allowed only because the Itanium architecture treats data dependencies and
the ordering semantics differently.
The ordering semantics require , but do not place any constraints on the
relative order of operations M1, M2, or M3. Due to the register and memory
dependencies between the instructions on Processor #0, these operations complete
in
program order on Processor #0 and also become locally visible in this order. However,
the operations need not be made visible to remote processors in program order. In this
outcome it appears to Processor #0 as if while to Processor #1 it appears that
There are two things to note here. First, the behavior is another example of
the local bypass behavior that Section 2.2.1.8 presents on page 2:518 . Second, there
are no dependencies directly between M1 and M3 that requires them to become
globally visible in program order.
Note: All processors will observe the order established by a particular processor in
case of a WAW memory dependency to the same location. For example, all pro-
cessors in the coherence domain eventually see a value of 1 in location x in the
following code:
st [x] = 0 // M1: set [x] to 0
st [x] = 1 // M2: set [x] to 1,
// cannot move above M1 due to WAW
because there is a WAW memory dependency between from M2 to M1
and the Itanium architecture requires that the local processor resolves
RAW, WAR, and WAW dependencies between its memory accesses in
program order. Thus,
even though the ordering semantics do
not place any constraints on the relative ordering of M1 and M2.
Table 2-5. Dependencies Do Not Establish MP Ordering (1)
Processor #0 Processor #1
st [x] = 1 ;; // M1
ld r1 = [x] ;; // M2
st [y] = r1 ;; // M3
ld.acq r2 = [y] // M4
ld r3 = [x] // M5
Outcomes: r1 = 1, r2 = 1, and r3 = 0 is allowed
M4 M5

M1 M3

M3 M1.

M1 M2
