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Volume 1, Part 1: Application Programming Model
The
flushrs
instruction is used to force all previous stack frames out to backing store
memory. It stalls instruction execution until all active frames in the physical register
stack up to, but not including the current frame are spilled to the backing store by the
RSE. A
flushrs
instruction must be the first instruction in an instruction group;
otherwise, the results are undefined. A
flushrs
cannot be predicated.
The
cover
instruction creates a new frame of zero size (sof = sol = 0). The new frame
is created above (not overlapping) the present frame. Both the local and output areas
of the previous stack frame are automatically saved. A
cover
instruction must be the
last instruction in an instruction group; otherwise, operation is undefined. A
cover
cannot be predicated.
The
loadrs
instruction ensures that the specified portion of the register stack is present
in the physical registers. It stalls instruction execution until the number of bytes
specified in the loadrs field of the RSC application register have been filled from the
backing store by the RSE (starting from the current BSP). By specifying a zero value for
RSC.loadrs,
loadrs
can be used to indicate that all stacked registers outside the
current frame must be loaded from the backing store before being used. In addition,
stacked registers outside the current frame (that have not been spilled by the RSE) will
not be stored to the backing store. A
loadrs
instruction must be the first instruction in
an instruction group otherwise the results are undefined. A
loadrs
cannot be
predicated.
lists the architectural visible state relating to the register stack.
summarizes the register stack management instructions. Call- and return-type
branches, which affect the stack, are described in
“Branch Instructions” on page 1:74
4.2
Integer Computation Instructions
The integer execution units provide a set of arithmetic, logical, shift and
bit-field-manipulation instructions. Additionally, they provide a set of instructions to
accelerate operations on 32-bit data and pointers.
Arithmetic, logical and 32-bit acceleration instructions can be executed on both I- and
M-units
Table 4-1.
Architectural Visible State Related to the Register Stack
Register
Description
AR[PFS].pfm
Previous Frame Marker field
AR[RSC]
Register Stack Configuration application register
AR[BSP]
Backing store pointer application register
AR[BSPSTORE]
Backing store pointer application register for memory stores
AR[RNAT]
RSE NaT collection application register
Table 4-2.
Register Stack Management Instructions
Mnemonic
Operation
alloc
Allocate register stack frame
flushrs
Flush register stack to backing store
loadrs
Load register stack from backing store
cover
Cover current stack frame
Содержание ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
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Страница 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 12: ...1 1 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Part I Application Architecture Guide ...
Страница 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Страница 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Страница 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Страница 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
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Страница 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 249: ...2 1 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Part I System Architecture Guide ...
Страница 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Страница 380: ...2 132 Volume 2 Part 1 Interruptions ...
Страница 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Страница 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Страница 749: ...2 501 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Part II System Programmer s Guide ...
Страница 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Страница 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Страница 808: ...2 560 Volume 2 Part 2 Context Management ...
Страница 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Страница 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Страница 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Страница 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
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Страница 941: ...3 42 Volume 3 Instruction Reference cmp illegal_operation_fault PR p1 0 PR p2 0 Interruptions Illegal Operation fault ...
Страница 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Страница 1191: ...3 292 Volume 3 Pseudo Code Functions Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
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Страница 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Страница 1564: ...4 262 Volume 4 Base IA 32 Instruction Reference LES Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1565: ...Volume 4 Base IA 32 Instruction Reference 4 263 LFS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1568: ...4 266 Volume 4 Base IA 32 Instruction Reference LGS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1583: ...Volume 4 Base IA 32 Instruction Reference 4 281 LSS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Страница 1663: ...Volume 4 Base IA 32 Instruction Reference 4 361 SHL SHR Shift Instructions See entry for SAL SAR SHL SHR ...
Страница 1668: ...4 366 Volume 4 Base IA 32 Instruction Reference SIDT Store Interrupt Descriptor Table Register See entry for SGDT SIDT ...
Страница 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Страница 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Страница 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...