2:352
Volume 2, Part 1: Processor Abstraction Layer
Scratch
When applied to either an entrypoint or procedure, scratch means that the contents of
the register has no meaning and need not be preserved. Further the register is
available for the storage of local variables. Unless otherwise noted, the register should
not be relied upon to contain any particular value after exit.
Stacked Calling Convention
The firmware calling convention which adheres fully to the Itanium Runtime Calling
Conventions. To use this calling convention, the RSE must be working and usable.
Static Calling Convention
The firmware calling convention which adheres to the Itanium Runtime Calling
Conventions for the static general registers, branch registers, predicate registers, but
for which all other registers are unused except for the RSE control registers. The RSE is
placed in enforced lazy mode, and the stacked general registers or memory are not
referenced.
System Abstraction Layer (SAL)
SAL is firmware that abstracts platform implementation differences for higher level
software. SAL has no knowledge of processor implementation details.
Unchanged
When applied to an entrypoint, unchanged means that the register referenced has not
been changed from the time of the hardware event that caused the entrypoint to be
invoked until it exited to higher level firmware or software. When applied to a
procedure, unchanged means that the register referenced has not been changed from
procedure entry until procedure exit. In all cases, the value at exit is the same as the
value at entry or the occurrence of the hardware event.
Virtual Machine Monitor (VMM)
The VMM is the system software which implements software policies to
manage/support virtualization of processor and platform resources.
Virtual Processor Descriptor (VPD)
Represents the abstraction of the processor resources of a single virtual processor. The
VPD consists of per-virtual-processor control information together with
performance-critical architectural state. See
Section 11.7.1, “Virtual Processor
Descriptor (VPD)” on page 2:325
for details.
Virtual Processor State
A memory data structure which represents the architectural state of a virtual processor.
Part of the virtual processor state is located in the Virtual Processor Descriptor (VPD),
and the rest is located in memory data structures maintained by the virtual machine
monitor.
11.9
PAL Code Memory Accesses and Restrictions
PAL issues load and store operations to memory in the following cases with the
following memory attributes:
• During machine check/INIT handling to the min-state save area memory region
registered with PAL using the UC memory attribute.
Содержание ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
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Страница 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 12: ...1 1 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Part I Application Architecture Guide ...
Страница 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Страница 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Страница 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Страница 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
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Страница 249: ...2 1 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Part I System Architecture Guide ...
Страница 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Страница 380: ...2 132 Volume 2 Part 1 Interruptions ...
Страница 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Страница 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Страница 749: ...2 501 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Part II System Programmer s Guide ...
Страница 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Страница 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Страница 808: ...2 560 Volume 2 Part 2 Context Management ...
Страница 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Страница 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Страница 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Страница 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
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Страница 941: ...3 42 Volume 3 Instruction Reference cmp illegal_operation_fault PR p1 0 PR p2 0 Interruptions Illegal Operation fault ...
Страница 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Страница 1191: ...3 292 Volume 3 Pseudo Code Functions Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
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Страница 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Страница 1564: ...4 262 Volume 4 Base IA 32 Instruction Reference LES Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1565: ...Volume 4 Base IA 32 Instruction Reference 4 263 LFS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1568: ...4 266 Volume 4 Base IA 32 Instruction Reference LGS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1583: ...Volume 4 Base IA 32 Instruction Reference 4 281 LSS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Страница 1663: ...Volume 4 Base IA 32 Instruction Reference 4 361 SHL SHR Shift Instructions See entry for SAL SAR SHL SHR ...
Страница 1668: ...4 366 Volume 4 Base IA 32 Instruction Reference SIDT Store Interrupt Descriptor Table Register See entry for SGDT SIDT ...
Страница 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Страница 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Страница 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...