Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Руководство пользователя

Страница: 514 / 1898

2:266 Volume 2, Part 1: Itanium
®
Architecture-based Operating System Interaction Model with IA-32 Applications
Per Table 10-7 , IA-32 memory references can be expressed in terms of acquire,
release, fence and sequential ordering rules defined by the Itanium architecture. IA-32
data memory references follow the same ordering relationships as defined for Itanium
architecture-based code as defined in
Section 4.4.7, “Sequentiality Attribute and
Ordering” on page 2:82 . The following additional clarifications need to be made for
IA-32 instruction set execution:
• IA-32 loads and instruction fetches to speculative memory can occur randomly.
Read accesses to speculative memory can occur at arbitrary times even if the
in-order execution of the program does not require a read or instruction fetch from
a given memory location.
• IA-32 instruction fetches and loads to non-speculative memory occur in program
order. IA-32 instruction cache line fetch accesses to uncached memory occur in the
order specified by an in-order execution of the program. Note however that the
same cache line may be fetched multiple times by the processor as multiple
instructions within the cache line are executed. The size of a cache line and number
of instruction fetches is model specific.
• IA-32 instruction fetches are not perceived as passing prior IA-32 stores. IA-32
stores into the IA-32 instruction stream are observed by the processor’s self
modifying code logic. Speculative instruction fetches may be emitted by the
processor before a store is seen to the instruction stream and then discarded. Self
modifying code due to Itanium stores is not detected by the processor.
• IA-32 instruction fetches can pass prior loads or memory fence operations from the
same processor. Data memory accesses, and memory fences are not ordered with
respect to IA-32 instruction fetches.
• IA-32 instruction fetches can not pass any serializing instructions, including Itanium
srlz.i
and IA-32 CPUID. For speculative memory types the processor may
prefetch ahead of a serialization operation and then discard the prefetched
instructions.
• IA-32 serializing operations wait for all previous stores and loads to complete, and
for all prior stores buffered by the processor to become visible. IA-32 serializing
instructions include CPUID.
• IA-32 OUT instructions may be buffered, however the processor will not start
execution of the next IA-32 instruction until the OUT has completed (been accepted
by the platform).
• The processor does not begin execution of the next IA-32 instruction until the IN or
OUT has been completed (accepted) by the platform. This statement does not apply
locked
or read-modify-write
operation sequential
fence
flush prior stores non-sequential
fence
flush prior stores non-sequential
fence
flush prior stores
IN, INS, OUT, OUTS sequential
fence
flush prior stores undefined undefined
IA-32 Serialization fence, flush prior stores
SFENCE release, flush prior stores
a. However, IA-32 loads/stores to uncacheable memory flush the write coalescing buffers.
b. However, IA-32 load/stores to cacheable memory do not flush the write coalescing buffers.
Table 10-7. IA-32 Load/Store Sequentiality and Ordering (Continued)
IA-32 Memory
Reference
Uncacheable
Write
Coalescing
Cacheable