Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Руководство пользователя

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2:82 Volume 2, Part 1: Addressing and Protection
• It takes an External interrupt, but if it had not taken an External interrupt, it would
have met one of the above qualifications (execute without fault, take an Unaligned
Data Reference fault, or take a Data Debug fault)
Data-speculative loads are treated the same as normal loads, and if an in-order
execution of the program requires the execution of a data speculative load, it
constitutes a verified reference. Control-speculative loads to limited-speculation pages
always defer and thus never constitute verified references.
It is not necessary for a processor to determine whether a reference will complete
without generating a machine check for it to be a verified reference. If software actually
references a physical address which will cause a machine check, hardware may
generate multiple speculative references to the same page, potentially causing multiple
machine checks.
Processors may access verified pages normally, as they would WB pages, including the
use of caching, pipelining and hardware-generate speculative references to improve
performance.
Calling the PAL_PREFETCH_VISIBILITY procedure forces the processor to clear the
storage holding the addresses of verified pages.
4.4.7 Sequentiality Attribute and Ordering
Memory ordering is defined in Section 4.4.7, “Memory Access Ordering” on page 1:73 .
This section defines additional ordering rules for non-cacheable memory, cache
synchronization (
sync.i
) and global TLB purge operations (
ptc.g
,
ptc.ga
).
As described in Section 4.4.7, “Memory Access Ordering” on page 1:73 ,
read-after-write, write-after-write, and write-after-read dependencies to the same
memory location (memory dependency) are performed in program order by the
processor. Otherwise, all other memory references may be performed in any order
unless the reference is specifically marked as ordered. No ordering exists between
instruction accesses and data accesses or between any two instruction accesses. IA-32
memory references follow a stronger processor consistency memory model.
See “IA-32
Memory Ordering” on page 2:265. for IA-32 memory ordering details. Explicit ordering
takes the form of a set of Itanium instructions: ordered load and check load (
ld.acq
,
ld.c.clr.acq
), ordered store (
st.rel
), semaphores (
cmpxchg
,
xchg
,
fetchadd
),
memory fence (
mf
), synchronization (
sync.i
) and global TLB purge (
ptc.g
,
ptc.ga
).
The
sync.i
instruction is used to maintain an ordering relationship between instruction
and data caches on local and remote processors. The global TLB purge instructions
maintain multiprocessor TLB coherence.
For VHPT walks, visibility is defined by the memory read(s) which retrieves translation
information, and the associated insertion of the translation into the TLB. VHPT walks
are performed asynchronously with respect to program execution, and each walker
VHPT read (which appears as though it were performed atomically) is made visible at
some single point in the program order. Ordering constraints from
Table 4-15 do not
prevent VHPT walks from becoming visible.