Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Руководство пользователя, Страница: 308 / 1898

2:60 Volume 2, Part 1: Addressing and Protection
Processor models have at least 16 protection key registers, and at least 18-bits of
protection key. Some processor models may implement additional protection key
registers and protection key bits. Unimplemented bits and registers are reserved. Key
registers have at least as many implemented key bits as region registers have rid bits.
Additional implemented bits must be contiguous and start at bit 18. Please see the
processor-specific documentation for further information on the number of protection
key registers and protection key bits implemented on the Itanium processor.
Software must issue an instruction serialization operation to ensure writes into the
protection key registers are observed by dependent instruction fetches and a data
serialization operation for dependent memory data references.
The processor ensures uniqueness of protection keys by checking new valid protection
keys against all protection key registers during the move to PKR instruction. If a valid
matching key is found in any PKR register, the processor invalidates the matching PKR
register by setting PKR.v to zero, before performing the write of the new PKR register.
The other fields in any matching PKR remain unchanged when it is invalidated.
Key Miss and Permission faults are only raised when memory translations are enabled
(PSR.dt is 1 for data references, PSR.it is 1 for instruction references, PSR.rt is 1 for
register stack references), and protection key checking is enabled (PSR.pk is one).
Data TLB protection keys can be acquired with the Translation Access Key (
tak
)
instruction. Instruction TLB key values are not directly readable. To acquire instruction
key values software should make provisions to read memory structures.
4.1.4 Translation Instructions
Table 4-8 lists translation instructions used to manage translations. Region registers,
protection key registers and the TLBs are accessed indirectly; the register number is
determined by the contents of a general register.
The processor does not ensure that modification of the translation resources is
observed by subsequent instruction fetches or data memory references. Software must
issue an instruction serialization operation before any dependent instruction fetch and a
data serialization operation before any dependent data memory reference.
Table 4-8. Translation Instructions
Mnemonic Description Operation
Instr.
Type
Serialization
Requirement
mov rr[ r
3
] = r
2
Move to region
register RR[GR[ r
3
]] = GR[ r
2
] M data/inst
mov r
1
= rr[ r
3
]
Move from region
register GR[ r
1
] = RR[GR[ r
3
]] M none
mov pkr[ r
3
] = r
2
Move to
protection key
register PKR[GR[ r
3
]] = GR[ r
2
] M data/inst
mov r
1
= pkr[ r
3
]
Move from
protection key
register GR[ r
1
] = PKR[GR[ r
3
]] M none
itc.i r
3
Insert instruction
translation cache ITC = GR[ r
3
], IFA, ITIR M inst