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2:30
Volume 2, Part 1: System State and Programming Model
Interruption
Control
Registers
CR16
IPSR
Interruption Processor Status Register
implied
CR17
ISR
Interruption Status Register
implied
c
CR18
reserved
CR19
IIP
Interruption Instruction Pointer
implied
d
CR20
IFA
Interruption Faulting Address
implied
CR21
ITIR
Interruption TLB Insertion Register
implied
CR22
IIPA
Interruption Instruction Previous Address
implied
CR23
IFS
Interruption Function State
implied
CR24
IIM
Interruption Immediate register
implied
CR25
IHA
Interruption Hash Address
implied
CR26
IIB0
Interruption Instruction Bundle 0
implied
CR27
IIB1
Interruption Instruction Bundle 1
implied
Reserved
CR28-63
reserved
Interrupt
Control
Registers
CR64
LID
Local Interrupt ID
data
CR65
IVR
External Interrupt Vector Register (read only)
data
CR66
TPR
Task Priority Register
data
a
CR67
EOI
End Of External Interrupt
data
CR68
IRR0
External Interrupt Request Register 0 (read only)
data
CR69
IRR1
External Interrupt Request Register 1 (read only)
data
CR70
IRR2
External Interrupt Request Register 2 (read only)
data
CR71
IRR3
External Interrupt Request Register 3 (read only)
data
CR72
ITV
Interval Timer Vector
data
CR73
PMV
Performance Monitoring Vector
data
CR74
CMCV
Corrected Machine Check Vector
data
CR75-79
reserved
reserved
CR80
LRR0
Local Redirection Register 0
data
CR81
LRR1
Local Redirection Register 1
data
Reserved
CR82-127
reserved
reserved
a. Serialization is needed to ensure external interrupt masking, new interval timer match values or new
interruption table addresses are observed before a given point in program execution.
b. Serialization is needed to ensure new values in PTA are visible to the hardware Virtual Hash Page Table
(VHPT) walker before a dependent instruction fetch or data access.
c. These registers are modified by the processor on an interruption or by an explicit move to these registers.
There are no side effects when written.
d. These registers are implied operands to the rfi and/or TLB insert instructions. The processor ensures writes in
previous instruction groups are observed by rfi and/or TLB insert instructions in subsequent instruction
groups. These registers are also modified by the processor on an interruption, subsequent reads return the
results of the interruption. There are no other side effects.
e. IFS written by a
cover
instruction followed by a move-from IFS is implicitly serialized.
Table 3-4.
Control Register Instructions
Mnemonic
Description
Operation
Format
mov
cr
3
=
r
2
Move to control register
CR[
r
3
]
GR[
r
2
]
M
mov
r
1
=
cr
3
Move from control register
GR[
r
1
]
CR[
r
3
]
M
Table 3-3.
Control Registers (Continued)
Register
Name
Description
Serialization
Required
Содержание ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Страница 1: ......
Страница 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 12: ...1 1 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Part I Application Architecture Guide ...
Страница 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Страница 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Страница 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Страница 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Страница 230: ......
Страница 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 249: ...2 1 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Part I System Architecture Guide ...
Страница 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Страница 380: ...2 132 Volume 2 Part 1 Interruptions ...
Страница 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Страница 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Страница 749: ...2 501 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Part II System Programmer s Guide ...
Страница 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Страница 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Страница 808: ...2 560 Volume 2 Part 2 Context Management ...
Страница 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Страница 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Страница 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Страница 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Страница 891: ......
Страница 941: ...3 42 Volume 3 Instruction Reference cmp illegal_operation_fault PR p1 0 PR p2 0 Interruptions Illegal Operation fault ...
Страница 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Страница 1191: ...3 292 Volume 3 Pseudo Code Functions Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Страница 1296: ......
Страница 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Страница 1564: ...4 262 Volume 4 Base IA 32 Instruction Reference LES Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1565: ...Volume 4 Base IA 32 Instruction Reference 4 263 LFS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1568: ...4 266 Volume 4 Base IA 32 Instruction Reference LGS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1583: ...Volume 4 Base IA 32 Instruction Reference 4 281 LSS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Страница 1663: ...Volume 4 Base IA 32 Instruction Reference 4 361 SHL SHR Shift Instructions See entry for SAL SAR SHL SHR ...
Страница 1668: ...4 366 Volume 4 Base IA 32 Instruction Reference SIDT Store Interrupt Descriptor Table Register See entry for SGDT SIDT ...
Страница 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Страница 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Страница 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...