Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Руководство пользователя, Страница: 278 / 1898

2:30 Volume 2, Part 1: System State and Programming Model
Interruption
Control
Registers CR16 IPSR Interruption Processor Status Register implied
d
CR17 ISR Interruption Status Register implied
c
CR18 reserved
CR19 IIP Interruption Instruction Pointer implied
d
CR20 IFA Interruption Faulting Address implied
d
CR21 ITIR Interruption TLB Insertion Register implied
d
CR22 IIPA Interruption Instruction Previous Address implied
c
CR23 IFS Interruption Function State implied
d,e
CR24 IIM Interruption Immediate register implied
c
CR25 IHA Interruption Hash Address implied
c
CR26 IIB0 Interruption Instruction Bundle 0 implied
c
CR27 IIB1 Interruption Instruction Bundle 1 implied
c
Reserved CR28-63 reserved
Interrupt
Control
Registers CR64 LID Local Interrupt ID data
a
CR65 IVR External Interrupt Vector Register (read only) data
a
CR66 TPR Task Priority Register data
a
CR67 EOI End Of External Interrupt data
a
CR68 IRR0 External Interrupt Request Register 0 (read only) data
a
CR69 IRR1 External Interrupt Request Register 1 (read only) data
a
CR70 IRR2 External Interrupt Request Register 2 (read only) data
a
CR71 IRR3 External Interrupt Request Register 3 (read only) data
a
CR72 ITV Interval Timer Vector data
a
CR73 PMV Performance Monitoring Vector data
a
CR74 CMCV Corrected Machine Check Vector data
a
CR75-79 reserved reserved
CR80 LRR0 Local Redirection Register 0 data
a
CR81 LRR1 Local Redirection Register 1 data
a
Reserved CR82-127 reserved reserved
a. Serialization is needed to ensure external interrupt masking, new interval timer match values or new
interruption table addresses are observed before a given point in program execution.
b. Serialization is needed to ensure new values in PTA are visible to the hardware Virtual Hash Page Table
(VHPT) walker before a dependent instruction fetch or data access.
c. These registers are modified by the processor on an interruption or by an explicit move to these registers.
There are no side effects when written.
d. These registers are implied operands to the rfi and/or TLB insert instructions. The processor ensures writes in
previous instruction groups are observed by rfi and/or TLB insert instructions in subsequent instruction
groups. These registers are also modified by the processor on an interruption, subsequent reads return the
results of the interruption. There are no other side effects.
e. IFS written by a
cover
instruction followed by a move-from IFS is implicitly serialized.
Table 3-4. Control Register Instructions
Mnemonic Description Operation Format
mov cr
3
= r
2
Move to control register CR[ r
3
]

GR[ r
2
] M
mov r
1
= cr
3
Move from control register GR[ r
1
]

CR[ r
3
] M
Table 3-3. Control Registers (Continued)
Register Name Description
Serialization
Required