Intel Itanium 9150M, Руководство пользователя

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Volume 3: Instruction Reference 3:157
ldf
ldf — Floating-point Load
Format: (
qp
) ldf
fsz
.
fldtype
.
ldhint f
1
= [
r
3
] no_base_update_form M9
(
qp
) ldf
fsz
.
fldtype
.
ldhint f
1
= [
r
3
],
r
2
reg_base_update_form M7
(
qp
) ldf
fsz
.
fldtype
.
ldhint f
1
= [
r
3
],
imm
9
imm_base_update_form M8
(
qp
) ldf8.
fldtype
.
ldhint f
1
= [
r
3
] integer_form, no_base_update_form M9
(
qp
) ldf8.
fldtype
.
ldhint f
1
= [
r
3
],
r
2
integer_form, reg_base_update_form M7
(
qp
) ldf8.
fldtype
.
ldhint f
1
= [
r
3
],
imm
9
integer_form, imm_base_update_form M8
( qp ) ldf.fill.
ldhint f
1
= [
r
3
] fill_form, no_base_update_form M9
(
qp
) ldf.fill.
ldhint f
1
= [
r
3
],
r
2
fill_form, reg_base_update_form M7
(
qp
) ldf.fill.
ldhint f
1
= [
r
3
],
imm
9
fill_form, imm_base_update_form M8
Description:
A value consisting of
fsz
bytes is read from memory starting at the address specified by
the value in GR
r
3
. The value is then converted into the floating-point register format
and placed in FR
f
1
. See Section 5.1, “Data Types and Formats” on page 1:85 for details
on conversion to floating-point register format. The values of the
fsz
completer are
given in Table 2-35 . The
fldtype
completer specifies special load operations, which are
described in Table 2-36 .
For the integer_form, an 8-byte value is loaded and placed in the significand field of FR
f
1
without conversion. The exponent field of FR
f
1
is set to the biased exponent for 2.0
63
(0x1003E) and the sign field of FR
f
1
is set to positive (0).
For the fill_form, a 16-byte value is loaded, and the appropriate fields are placed in FR
f
1
without conversion. This instruction is used for reloading a spilled register. See
Section 4.4.4, “Control Speculation” on page 1:60 for details.
In the base update forms, the value in GR
r
3
is added to either a signed immediate
value (
imm
9
) or a value from GR
r
2
, and the result is placed back in GR
r
3
. This base
register update is done after the load, and does not affect the load address. In the
reg_base_update_form, if the NaT bit corresponding to GR
r
2
is set, then the NaT bit
corresponding to GR
r
3
is set and no fault is raised.
Table 2-35. fsz Completers
fsz Completer Bytes Accessed Memory Format
s 4 bytes Single precision
d 8 bytes Double precision
e 10 bytes Extended precision
Table 2-36. FP Load Types
fldtype
Completer
Interpretation Special Load Operation
none Normal load
s Speculative load Certain exceptions may be deferred rather than generating a fault.
Deferral causes NaTVal to be placed in the target register. The NaTVal
value is later used to detect deferral.
a Advanced load An entry is added to the ALAT. This allows later instructions to check for
colliding stores. If the referenced data page has a non-speculative
attribute, no ALAT entry is added to the ALAT and the target register is
set as follows: for the integer_form, the exponent is set to 0x1003E and
the sign and significand are set to zero; for all other forms, the sign,
exponent and significand are set to zero. The absence of an ALAT entry
is later used to detect deferral or collision.