Dual-Core Intel
®
Itanium
®
Processor 9000 and 9100 Series Datasheet
21
Electrical Specifications
T
rise
BCLKp Rise Time
7
All
333
500
667
ps
Figure 2-1
20–80%
T
fall
BCLKp Fall Time
7
All
333
500
667
ps
Figure 2-1
20–80%
V
PP
Minimum Input Swing
All
600
mV
Figure 2-1
6
Notes:
1. The system clock skew is ±100 ps.
2. Measured on cross-point of rising edge of BCLKp and falling edge of BCLKn. Long-term jitter is defined as peak-to-peak variation
measured by accumulating a large number of clock cycles and recording peak-to-peak jitter.
3. Cycle-to-cycle jitter is defined as peak-to-peak variation measured over 10,000 cycles peak-to-peak jitter.
4. Measured on cross point of rising edge of BCLKp and falling edge of BCLKn.
5. The system clock skew is ±60 ps.
6. V
PPmin
is defined as the minimum input differential voltage which will cause no increase in the clock receiver timing.
7. The measurement is taken at 40-60% of the signal and extrapolated to 20-80%.
Table 2-11. SMBus AC Specifications
Symbol
Parameter
Minimum
Maximum
Unit
Notes
f
SMSC
SMSC Clock Frequency
100
kHz
T
SMSC
SMSC Clock Period
10
µs
t
high
SMSC Clock High Time
4.0
µs
1
Notes:
1. Please refer to
Figure 2-2
for the Standard Microsystems Corporation (SMSC)* clock waveform.
t
low
SMSC Clock Low Time
4.7
µs
1
t
rise
SMSC Clock Rise Time
1.0
µs
1
t
fall
SMSC Clock Fall Time
0.3
µs
1
t
VALID
SMBus Output Valid Delay
1.0
µs
t
SU
SMBus Input Setup Time
250
ns
t
HLD
SMBus Input Hold Time
0
ns
t
FREE
Bus Free Time
4.7
µs
2
2. Bus Free Time is the minimum time allowed between request cycles.
Figure 2-1.
Generic Clock Waveform
000615
Table 2-10.System Bus Clock Differential HSTL AC Specifications (Sheet 2 of 2)
Symbol
Parameter
System
Bus
Clock
(MHz)
Minimum
Typ
Maximum
Unit
Figure
Notes
80%
T
rise
T
rise
Rise Time
T
fall
Fall Time
High Time
T
high
Low Time
T
low
=
=
=
=
20%
T
fall
T
high
T
low
T
period
T
jitter
BCLKN
BCLKP
V
pp
=
T
period
Period
T
jitter
Long Term Peak-to-Peak Jitter
Peak-to-Peak Swing
=
=
=
V
pp
Содержание Itanium 9010
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