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Содержание iSBC 432/100

Страница 1: ...inter iSBC 432 100 Processor Board Hardware Reference Manual PN 171820 001 ...

Страница 2: ...I I 11 I iSBC 432 100 PROCESSOR BOARD HARDWARE REFERENCE MANUAL Manual Order Number 171820 001 Copyright 1981 Intel Corporation Intel Corporation 3065 Bowers Avenue Santa Clara California 95051 11 11 I ...

Страница 3: ...r the use of any circuicry other than circuitry embodied in an Intel product No other circuit patent licenses are implied Intel software products are copyrighted by and shall remain the property of Intel Corporation Lse duplication or disclosure is subject to restrictions stated in Intel s software license or as defined in ASPR 7 104 9 a 9 No part of this document may be copied or reproduced in an...

Страница 4: ...860 001 Intel 8251 Universal Synchronous Asynchronous Receiver Transmitter Appiication Note AP i6 Intel Multibus Specification Order No 9800683 Intel Multibus Interfacing Application Note AP 28 Introductory iAPX 432 information if required is contained in the following documents The iAPX 432 Object Primer Order No 171858 001 Introduction to the iAPX 432 Architecture Order No 171821 001 GettingStar...

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Страница 6: ...Command Instruction Format 3 4 Reset 3 4 Addressing 3 4 Initialization 3 4 CONTENTS PAGE Operation 3 5 Data Input Output 3 5 Status Read 3 5 8253A PIT Programming 3 5 Mode Control Word and Count 3 6 Addressing 3 8 Initialization 3 8 Operation 3 9 Counter Read 3 9 Clock Frequency Divide Ratio Selection 3 9 Synchronous Mode 3 9 Asynchronous Mode 3 9 iSBC 432 100 Control and Status Registers 3 10 CHA...

Страница 7: ...PIT Mode Control Word Format 1 1 2 9 2 10 2 10 2 11 3 3 3 3 3 3 3 3 3 4 3 5 3 6 3 7 TABLE 2 8 2 9 3 1 3 2 5 1 5 2 TABLES TITLE PAGE Serial l O Connector J1 Pin Assignments 2 12 Connector J 1vs RS 232 C Pin Correspondence 2 12 iSBC 432 100 l O Address Assignments 3 2 PIT Count Value vs Rate Multiplier for Each Baud Rate 3 10 Replaceable Parts 5 2 List of Manufacturers Codes 5 3 ILLUSTRATIONS FIGURE...

Страница 8: ...mory and 1 0 operations CHAPTER 1 GENERAL INFORMATION An RS 232 C compatible serial 110 port controlled by an Intel 8251A USART Universal Synchronous Asynchronous Receiver Transmitter operates with standard CRT terminals at baud rates from 110 to 19 2K bits second The USART is individually pro grammable for operation in many synchronous and asynchronous serial data transmission formats including I...

Страница 9: ...ng and receiving devices only This design prevents slower master modules from being handicapped in their attempts to iSBC 432 100 gain control of the bus but does not restrict the speed at which faster modules can transfer data over the same bus 1 3 EQUIPMENT SUPPLIED The following items are supplied with the iSBC 432 100 Processor Board a Schematic diagram drawing no 171773 b Assembly drawing dra...

Страница 10: ...z may be generated utilizing the on board crystal oscillator and 16 bit PIT 1 228 MHz 0 1 82 micmsecond nominai period Rate Generator 37 5 Hz to 614 4 kHz Process Clock 3 25 microseconds to 58 25 minutes cascaded timers On board 1 0 devices recognize an 8 bit 1 0 address iSBC 432 100 local accesses are translated to Multibus 1 0 accesses EIA standard RS 232 C signals provided and supported Clear t...

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Страница 12: ...se as a bus master in an lntellec 800 Intellec Series II or Intellec Series III Microcomputer Development System Important criteria for installing and interfacing the iSBC 432 100 board in this configuration are presented in the following paragraphs Table 2 1 Connector Details No of Pairs Centers Connector Intel Function Pins inches Type Vendor Vendor Part No Part No Serial 13 26 0 1 Flat Crimp 3M...

Страница 13: ...n board 1 0 ports The default jumper 79 80 configures the 110 addresses to 1X The value of X is determined by the 1 0 port to be addressed refer to table 3 1 Other base addresses are selected as follows address jumper 7X 67 68 6X 69 70 5X 71 72 4X 73 74 3X 75 76 2X 77 78 1X 79 80 XACK Timing 1B8 3A6 The factory default jumper 54 55 provides the correct XACK delay to read and write on board 1 0 por...

Страница 14: ...se three inputs are read throuqh the processor status port These inputs appear on the three most significant data lines as follows Port Associated Data Bit Jumper 0 1 07 40 41 remove jumper install jumper 06 38 39 remove jumper install jumper 05 36 37 remove jumper install jumper In normal operation default jumper 43 44 the GDP is initialized when a Multibus master writes an initialization pattern...

Страница 15: ...2 100 board lllDS is an ordering code only and is not used as a product name or trademark MOS is a registered trademark of Mohawk Data Sciences Corp 2 4 iSBC 432 100 2 11 MULTIBUS BUS CONFIGURATION For system applications the iSBC 432 100 board is designed for installation in a standard Multibus backplane e g an Intellec Microcomputer Develop ment System Multibus signal characteristics and methods...

Страница 16: ...INH1 Inhibit RAM 67 DAT6 25 68 DAT 26 69 DAT4 27 BHEN Byte High Enable 70 DAT5 28 ADR10 Address bus bit 10 71 DAT2 29 CBRQ Common Bus Request 72 DAT3 30 AOR11 Address bus bit 11 73 DATO 31 CCLK Constant Clock 74 DAT1 32 ADR12 Address bus bit 12 75 GND Ground 33 INTA Interrupt Acknowledge 76 GND 34 ADR13 Address bus bit 13 77 35 INT6 Interrupt request on levern 78 36 INT Interrupt request on level ...

Страница 17: ...clock signal of constant frequency for use by other system modules CCLK is approximately 10 MHz with a worst case 35 65 percent duty cycle DATO DATF Data These 16 bidirectional data lines transmit data to and receive data from the addressed memory location or 1 0 port DATF is the most significant bit For data byte operations DATO DAT7 is the even byte and DAT8 DATFI is the odd byte INH1 Inhibit RA...

Страница 18: ...IL Input Low Voltage 0 8 v VIH Input High Voltage 2 0 v Ill Input Current at Low V VIN 0 45V 0 5 mA llH Input Current at High V VIN 5 5V 60 µA BPRO BREQ Vol Output Low Voltage loL 10 mA 0 45 v VoH Output High Voltage loH 0 4 mA 2 4 v BUSY CBRQ Vol Output Low Voltage loL 20 mA 0 45 v OPEN COLLECTOR DATO DATF Vol Output Low Voltage loL 32 mA 0 45 v VoH Output High Voltage loH 5 mA 2 4 v VIL Input Lo...

Страница 19: ... XACK samples toHR 0 Read data hold time toxL 400 Read data setup to XACK txAH 0 XACK hold time tBs 23 BPRN to BCLK setup time toBY 55 BCLK to BUSY delay tNOD 30 BPRN to BPRO delay toBo 40 BCLK I to bus priority out tBcv 100 Bus clock period BCLK tBw 35tBcv 65tBcv Bus clock low or high interval Supplied by system tiNIT 3000 Initialization width After all voltages have stabilized Table 2 7 iSBC 432...

Страница 20: ...paration for Use I tt J tas 7 _J 1 ____ r ____ l 1DBY l 1Dao 7 STABLE ADDRESS 7 J TABLE DATA x T IAS IDS ____r _ _ _ _ 1____ i AH DHW w _ tcMDw 4 r ____ ____________ 7 IACKWT u __J k txAH STABLE DATA IDXL r 1 I L DHR CBRQ timing not shown relative to other bus signals other than BCLK Figure 2 1 Bus Exchange Timing Master Mode 171820 2 2 9 ...

Страница 21: ...N I I BPRO IAS STABLE ADDRESS IACK IACC tDs STABLE DATA Figure 2 2 1 0 Access Timing Read Write J3 15 BPRN 16 16 BPRO c E LOWEST PRIORITY MASTER J4 15 BPRN BPRO 16 H iSBC432 100 IAH IOHW x BPRO AND BPRN PINS NOT USED BY NON MASTERS I I BACKPLANE I I 171820 3 L_ _j Figur 2 3 Serial Priority Resolution Scheme 171820 4 2 10 ...

Страница 22: ...st and two lowest priority bus masters are shown installed in the system backplane In the scheme shown in figure 2 4 the priority encoder is a 74148 and the priority decoder is an Intel 8205 Input connections to the priority encoder deter mine the bus priority with input 7 having the highest priority and input 0 having the lowest priority the 15 bus master has the lowest priority IMPORTANT In a pa...

Страница 23: ...26 pins whereas the RS 232 C connector has 25 pins Conse quently when connecting the 26 pin mating connec tor to 25 conductor flat cable be sure that the cable makes contact with pins 1 and 2 of the mating con nector and not with pin 26 Table 2 9 provides pin correspondence between the board edge connector JI and an RS 232 C connector When attaching the cable to JI be sure that the PC connector is...

Страница 24: ... Multibus transfer a bus lock feature permits the processor board to retain Multibus control for the complete sequence of Multibus transfers This feature eliminates the time required to release and regain bus control between data transfers thereby increasing throughput and lowering Multibus band width requirements 3 3 1 0 ADDRESSING AND ACCESS GDP local address references are translated into Multi...

Страница 25: ...ommand active 4 fatal error 5 7 user selectable jumpers XE w Processor Control bit description 0 release processor from initialized state 1 issue Multibus interrupt 2 issue interprocessor com munication request 3 stop GDP accesses 4 issue alarm signal Note Xis jumper selectable 1 7 as described in table 2 2 written into the USART sync characters or com mand instructions may be inserted The Mode in...

Страница 26: ... 1 0 1 0 0 1 1 SYNC llXI 116XI 164XI MODE CHARACTER LENGTH 0 1 0 1 0 0 1 1 s 6 7 8 BITS BITS BITS BITS l L ABLOE DISABLE EVEN PARITY GENERATION CHECK 1 EVEN O ODD NUMBER OF STOP BITS 0 1 0 1 0 0 1 1 INVALIO 1 2 BIT BITS BITS ONLY EFFECTS TX RX NEVER REQUIRES MORE THAN ONE STOP BIT Figure 3 3 USART Asynchronous Mode Instruction Word Format 111820 8 GENERATED TRANSMITTER OUTPUT Do D1 Dx BY 8251A I S...

Страница 27: ...ctions can be written to the USART at any time after one or more data operations After initialization always read the chip status and check for the TXRDY bit prior to writing either data or command words to the USART This ensures that any prior input is not overwritten and lost Note that issuing a Command instruction with bit 6 IR set will return the USART to the Mode instruction format 3 9 RESET ...

Страница 28: ... for the above are summarized in the following paragraphs NOTE After the USART has been initialized always check the status of the TXRDY bit prior to writing data or writing a new com mand word to the USART The TXRDY bit must be true to prevent overwriting and subsequent loss of command or data words The TXRDY bit is inactive until initializa tion has been completed do not check TXRDY until after ...

Страница 29: ...counter must be entered in the follow ing sequence a Mode control word b Least significant count register byte c Most significant count register byte l DSR lSYNDETI FE I OE I PE l TXE l RXRDY l TXRDY l L__ OVERRUN ERROR 4TRANSMITTER READY The OE flag is set when the CPU does Indicates USART is ready lo accept a not read a character before the next data character or command one becomes available It...

Страница 30: ...e programmed at any time following the mode control word as long as the correct number of bytes is loaded in order The count mode selected in the control word controls the counter output As shown in figure 3 8 the PIT chip can operate in any of six modes a mode 0 Interrupt on terminal count b mode I Programmable one shot c mode 2 Rate generator d mode 3 Square wave generator e mode 4 Software trig...

Страница 31: ...from one output pulse to the next equals the number of input counts in the count register If the count register is reloaded between output pulses the pres ent period will not be affected but the subsequent period will reflect the new value When mode 2 is set the output of the counter will remain high until after the couTtt register is loaded 3 17 ADDRESSING As listed in table 3 1 the PIT uses four...

Страница 32: ...ounter Register Latch Control Word Format 1 1s20 15 Programming Information 3 21 CLOCK FREQUENCY DIVIDE RATIO SELECTION To operate the 8251A serial I O port counter 2 must be loaded with a down count value N When count value N is loaded into a counter it becomes the clock divisor To derive N for either synchronous or asyn chronous RS 232 C operation use the procedures described in following paragr...

Страница 33: ...ser Selectable Jumpers Three flags that may be individually selected by the user IMPORTANT The Fatal Error signal is connected to a red LED in the upper left corner of the processor board When this LED is lit a fatal error has occurred and the GDP has suspended execution The iSBC 432 100 processor must be re initialized to continue execution The processor control register contains five software co...

Страница 34: ... transfer mode data reads and writes are performed one byte at a time over the Multibus bus In the 16 bit mode data reads and writes are performed as follows 1 When a single byte transfer is requested an 8 bit Multibus read or write is performed 2 When a multibyte transfer is requested on an even byte boundary the appropriate number of 16 bit Multibus transfers is performed 3 When a multibyte tran...

Страница 35: ... multiplexed address data bus The two clock phases CLKA and CLKB control the 43201 43202 timing The GDP interfaces with external logic by means of the 16 bit multiplexed address data bus the packet bus or ACD bus All external logic tim ing is synchronous with clock transitions Most input signals are sampled by the processor on the rising edge of CLKA inputs on the ACD bus are sampled on the fallin...

Страница 36: ...tes from the ACD bus If the read or write data is a single 8 bit data element it appears on the least significant bits of the 16 bit ACD bus The external circuitry may request that the processor hold stretch an access until the data is accepted for a write access or until the data is supplied for a read access by the external component s The ISB signal is used by the external circuitry to indicate...

Страница 37: ...ested by the processor this byte is transferred from the least significant eight Multibus data lines DATO DAT7 through a transparent latch A54 to the 4 4 least significant byte of the ACD bus ACDO ACD7 as illustrated in figure 4 5a When more than one byte is requested two 8 bit Multibus operations are combined into a single 16 bit processor transfer The first Multibus read latches DATO DAT7 into t...

Страница 38: ...FI FIRST MULTIBUS TRANSFER LOW BYTE IS LATCHED IN A54 DATo 7 DAT8 FI SECOND MULTIBUS TRANSFER HIGH BYTE FROM BUS LOW BYTE FROM LATCH t DATo 7 B DOUBLE BYTE READ TRANSFER 8 BIT MODE DAT8 FI DATo 7 C SINGLE BYTE WRITE TRANSFER 8 BIT MODE Figure4 5 iSBC 432 lOOrM Data Transfer Routing to from the Multibus Bus 171820 20 4 5 ...

Страница 39: ...COND MULTIBUS TRANSFER HIGH BYTE D DOUBLE BYTE WRITE TRANSFER 8 BIT MODE E SINGLE BYTE READ TRANSFER ODD ADDRESS 16 BIT MODE F SINGLE BYTE READ TRANSFER EVEN ADDRESS 16 BIT MODE iSBC 432 100 Figure 4 5 iSBC 432 100 Data Transfer Routing to from the Multibus Bus Cont d 111820 20 4 6 ...

Страница 40: ...d for process timing Counters 0 and 1 are cascaded to provide the process clock PCLK signal Counter 2 generates a programmable baud rate for the 8251A serial 1 0 port Baud rates from 110 to 19 2K are easily generated as discussed in paragraph 3 20 and table 3 2 4 9 SERIAL I O The 8251A USART provides an RS 232 C compat ible serial synchronous or asynchronous data link for CRT terminal operation Ch...

Страница 41: ...s on the board by a 4 8 iSBC 432 100 separate 50 ohm line driver A3 at 5C5 CLKA controls the timing of the address counters the transfer counter and the data transfer state machine The 110 clock is developed by an 8284 clock generator A41 at 3D6 and crystal Yl 14 7456 MHz This frequency is internally divided by six within the 8284 to provide a 2 4576 MHz master clock to the 8251A USART A21 at 3C4 ...

Страница 42: ...T E RR_ ___ X BOUT INTERPROCESSOR COMMUNICATION REQUEST WINDOW Figure 4 6 Typical Processor Write Cycle Timing 171820 21 CLKA ACD ADDRs 23 READ ISA ISB ____ s_T E R_R___ J BOUT INTERPROCESSOR COMMUNICATION REQUEST WINDOW Figure 4 7 Typical Processor Read Cycle Timing 171820 22 4 9 ...

Страница 43: ...ransfer request signal Interprocessor communication request from A23 at 4C6 BXACK Synchronized Muitibus XACK sigr1ai STOPRQ Processor access stop request from A26 at4C6 PINITI Processor initialization signal CNT1 Last byte transfer indicator AO Odd even address flag least significant address bit WRITE Processor write transfer indicator 4 10 During each state transition clock cycle one of the follo...

Страница 44: ...nd 16 bit data transfer proceed from state 2 to state l in the same manner as the events proceeded for the first transfer During this second transfer CNTI changes from low to high immediately following the transfer counter incre mentation between state 14 and state 1 Once in Principles of Operation state 1 ISB is set to zero indicating a second error free transfer and the state machine reenters th...

Страница 45: ...Principles of Operation 4 12 CMD NOOP ISB O CMD NOOP ISB O Figure 4 9 Data Transfer State Machine State Diagram iSBC 432 100 171820 24 ...

Страница 46: ...K 1 WDONE 0 COUNT Byte write stretch write access to CNT1 1 satisfy hold time WRITE 1 ACC BXACK 1 DRDONE 1 COUNT Double byte read access complete CNT1 0 AO O WRITE O ACC BXACK 1 DWDONE 0 COUNT Double byte write stretch write CNT1 0 access to satisfy hold time AO O WRITE 1 ACC BXACK 1 HWAIT 0 COUNT Odd access boundary perform one CNT1 0 byte at a time A0 1 HWAIT 10 BXACK 1 HWAIT 0 NOOP Wait until B...

Страница 47: ...nsfers see paragraph 2 10 and table 2 2 The bus lock con dition is invoked by driving the bus arbiter LOCK pin low The bus lock capability is enabled by a user selectable jumper option A30 at 2A6 4 14 iSBC 432 100 4 18 1 0 OPERATION The following paragraphs describe on board 1 0 operations All on board 1 0 devices are accessible only from the Multibus bus The actual functions performed by specific...

Страница 48: ...boards this number is usually silk screened onto the board On other MCSD products it is usually stamped on a label c Serial number of product On boards this number is usually stamped on the board On other MCSD products the serial number is usually stamped on a label d Shipping billing addresses e If your Intel product warranty has expired you must provide a purchase order number for billing purpos...

Страница 49: ...r SN74LS164 Tl 1 A38 IC 74LS175 Quad D Flip Flops SN74LS175 Tl 1 A18 24 25 IC 74LS273 Octal D Flip Flops SN74LS273 Tl 3 A15 16 IC 74LS283 4 Bit Full Adders SN74LS283 Tl 2 A44 IC 74LS367 Hex Bus Drivers SN74LS367 Tl 1 A4 39 IC 74SOO Quad 2 lnput NANO Gates SN74SOO Tl 2 A13 IC 74S08 Quad 2 lnput AND Gates SN74S08 Tl 1 A28 40 IC 74S32 Quad 2 lnput OR Gates SN74S32 Tl 2 A1 30 IC 74S74 Dual D Flip Flop...

Страница 50: ... Wire Wrap Plug Shorting 2 Position Mfr Part No 08D 08D 08D 514 AG19D 524 AG11D 528 AG11D 827 0067 00 CY148 105UL 89531 6 530153 2 Table 5 2 List of Manufacturers Codes Manufacturer AMP Inc Augat Inc Calmark Corporation Crystek Intel Corporation Motorola Semiconductor Signetics Texas Instruments Order by Description available from any commerical COML source Reference Information Mfr Qty Code COML ...

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Страница 52: ... CONN HSS RCPr LOC1 TI0 15 CHM T 8 7 6 6PL I 43201 po r CJ 0 i Vlp Clo 0 c 0 C A32 0 Ci G 0 _ J o ii h L 0 0 A3 i6 0 0 C q__ S 6 0 I I I 43202 5 2 bPL I 0 n01 l C c c1 _cr i 1 f 21 14Fl f PL CJ _f C 0 c c 0 C A54g COi 1 1PONENT S D 5 o 4 C 3 3 c p 4 3 2 n n n n n 1 REV DESCRIPTION DrT JUUUUULlWX ALL ITDA45 414J4H SECTION A A ALE NO E r AS9 _ q All CJ u po _ r l 0 QUANTITY PER DASH NC UNLESS OTHERW...

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Страница 54: ...LE A 1 75188 7 I A41 82eA 18 A1 f 2 0 A51 P 53 55 82137 10 eo ec ee 10 e D 7 14 7 14 7 14 7 14 A5 AS8 74LS10 7 14 Al A30 74574 7 14 l A 22 A 2 Ai h 7 L5 7 o l4 1 11 P 2 74L5125 7 14 A 37 74 5 139 e 6 A2 A3 7 1 5140 7 14 741 5175 e Ale Ac A25 74 l 5273 10 20 1 15 A16 74LS20 3 e 1 Ale A43 QUANTITY PER DUH NO UNLESS OTHERWISE SPECIFIED DIMEllSIOHS ARE IN I BREAK All SHMP DD NOT Wll IG xx 113 010 SURF...

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Страница 56: ... 1 74 532 AA tr I HD Rf l 3 I RPl 5 Eiff oEG l Jo EGG E65 EG l P w f RFQi 7 t i EfflNPc i p 8 l S JOB e IBl h_ll SeJ C ht th J 1 i b X AENt J 8 7 6 5 4 3 13 Al3 II 1e 508 513 7 14 A r e T Zlf 13 SI Yf r 11 1 2 0 re 15 9 EN Y3 532 L___J 4 nE E 4 5 32 rE 35 VCCI crrJ T10 A 4 9 74 7 I Ds g7 3 7 1 2 XJ Ee2 _ _ _E 01 E83 EM EeS 4 3 DWG NO 171959 DESCRIPTION DRAWN R UNt E TT ISSUED 2 REVISIOftS Df T CHK...

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Страница 58: ... llO 171959 f 5V l LS7 t 5AaQ RP3 4 ICC 2 I Uo D e_ A rr I 5 Q SW L___ RP3 3 1 L _ _ 7Sl8 A II f r J 13 1 32 P3 IZ C 15 I 3 l PF 5l JJ lE 31 rt 8C51A 8 1 J All I A 2 cl 7 1e6 L51Z 4 1QJ 5 8 10 wrl TXE t e P3 1 ti IrJl Tl 7518 A E 27 IOD el T i PEfl QE 28 IODf 7 v ODS 05 Ri C I 75iffi v IOD4 504 v 1003 e D3 v A Vil 4 __P3 OD 2 I i e v IOD I DI 1 J7 5 7518 JA E3 v roo 27 00 J S 4 v All b P rl 5 4 e ...

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Страница 60: ...QI s IPC Rt i l1 j 08 Q5 5 I4 I_O_D 2 2 D i D4 Q4 7 1 6 I 3 F3 v I I Q D5 QS l2 7 12 Fi 4C1 U PC 1 l R Qp6 QG 15 e I1 Fl L 17 D7 Q7lb l 10 F0118 SCI CLK AJ1 o_ Q l 9 lf if5V rSV 5V 7 1 10E ea37 fi 13 3M WDX 51 7 T j __ H 8 1 0 D 6 __ 1 hiW _tl tolr 1 _ _ QIA3 n 1 E 1 1 __ r o D 5 1 7_ A5 5583 I 0 D 4 1 8 M Mp12 10 D 3 __ 1 4 A 3 1331Ju 1i _ __ ___ I ill D 2 1 3 N eep nl_7___ l __ 1______11 J l r I...

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Страница 62: ... I 1 4 5 15 1 9 j So SS 14 IO 13 II rz rz II 13 1 14 9 IE e 7 18 E IC s zo 4 ZI 3 z z 2 23 Z4 s 54 53 52 SI 4 48 41 46 45 44 43 4 3 13 14 s 12 156 ISA PC LI BDJI z I 1S 14 3 11 A Q II 43202 10 8 MASTER 7 Ht R R IN E s 4 3 z 4 4 B 35 3 1 SV VC C3 3 1 1 I DWG NO OFT CHK DATE Al l llOVE CLK Aj IDS E De 2 C B 4D8 CLKA 4C B IS ISA 1 38 e ouT eour CJ Ke CLKA AC D 2 ACD I AC DZ ACD 3 AC D 4 A CD 5 ACD6 A...

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Страница 64: ... OB i Xl2 D QD U 4 L5lb3 ACD P _ 14 A Q 13 ACD I B QB ACD 2 5 0 12 ACD 3 E 9 l 5lb3 ti LD R C 15 A CD4 3 A QA 4 KD S 4 B QB 13 ACD6 5 c Cf 12 ACD 7 D QD II I L_J ACD P _ 4 LDA id LS 1b3 3 I QA 14 ACD I 4 B QB 13 ACD 2 5 c 2 ACD 3 D QD II VCC3 E 4 3 OWG NO 171959 REVISIONS ZONE REV DESCRIPTION I 11 I _ 196 83 C DI Ql e 3 Q 02 7 4 D3 Q3P 2 4 Q4 5 DS OS t o t 07 a F ee83 7 rx P 8 D7 Q pl2 5 D4 Q4p15 ...

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Страница 66: ... C D 6 I__ A f 4 p DAT l A C D 5 ___c 4 A B 3 hl6 DAi S r AC D 4 3 4 A C BZ 17 DAI 4 A C D c 3 1 AE eE hl3 DAT 3 A C D _ Z ____ 8 Al Bl 2 CV T if 1 _A C D 1 S A 4 541 JS CAT J A C D E AS BS 4 DA T jJ 4 rr 6 1 1 g r AS2 ri OE BZ Bl _ 4 i 1LSlw l I T A C D IS Z Al Bl pl8 DAi 7 ACD 14 I A B p DAT_ _ ACD 13 4 A7 83 t E DP i S ACD 12 3 A Z B Z hil DA I 4 ACD I I 7 6 86 13 DAT 3j ACD l f 8 Al Bl hl Z DA...

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Страница 68: ...mation you expected or required Please make suggestions for improvement 3 Is this the right type of document for your needs Is it at the right level What other types of documents are needed 4 Did you have any difficulty understanding descriptions or wording Where 5 Please rate this document on a scale of 1 to 10with10 being the best rating NAME ___________________________________________ DATE ____...

Страница 69: ...h reply will be carefully reviewed by the responsible person All comments and suggestions become the property of Intel Corporation BUSINESS REPLY MAIL FIRST CLASS PERMIT NO 1040 SANTA CLARA CA POSTAGE WILL BE PAID BY ADDRESSEE Intel Corporation Attn Technical Publications M S 6 2000 3065 Bowers Avenue Santa Clara CA 95051 NO POSTAGE NECESSARY IF MAILED IN U S A ...

Страница 70: ...INTEL CORPORATION 3585 S W 198th Avenue Aloha Oregon 97007 503 681 8080 Printed in U S A Y36 1 K 0281 IH ...

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