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Customer Reference Board Manual

Intel® IQ80333 I/O Processor

Hardware Reference Section

3.9.6

Detail Descriptions of Switches/Jumpers

3.9.6.1

Switch S1C2: Intel

80333 I/O Processor Reset

This switch resets 80333.

3.9.6.2

Switch S6A1: BPCI-X Reset

This switch resets the PCI-X B segment bus.

3.9.6.3

Switch S8A1: Rotary

For more information, please see

Section 3.6.6, “Rotary Switch” on page 33

3.9.6.4

Switch S7A1

This 10 pin switch that allows the user to enable or disable various features. Please see specifics
below.

3.9.6.4.1

S7A1-1: PCI-X Bus A Speed Enable Corresponding to
Signal Name PBI_AD3

This switch allows the user to force the PCI-X bus A to run at 133 MHz or 100 MHz.

3.9.6.4.2

S7A1-2: Reset I/O Processor Core Corresponding to
Signal Name PBI_AD5

RESET MODE is latched at the de-asserting edge of P_RST# and it determines when the 80333 is held
in reset until the Intel XScale

core Reset bit is cleared in the PCI Configuration and Status Register.

Table 20.

Rotary Switch Settings

Position

Description

Factory Default

Enables private devices on the secondary PCI-X slot. Redboot uses this setting to configure
private devices

Disables private devices on the secondary PCI-X slot. This setting allows the host to see all
the devices on the secondary PCI bus.

2-F

These settings are meaningless to Redboot. Other applications may use these settings for
configuration or software utilization.

Table 21.

S7A1-1: PCI-X Bus A Speed Enable

S7A1-1

Operation Mode

Open

Enables 133 MHz on PCI-X bus A

Closed

Enables 100 MHz on PCI-X bus A (Default Mode)

Содержание IQ80333

Страница 1: ...Intel IQ80333 I O Processor Customer Reference Board Manual February 2005 Document Number 306690001US Intel Part Number C90183 001 ...

Страница 2: ...PROPOSAL SPECIFICATION OR SAMPLE Intel disclaims all liability including liability for infringement of any proprietary rights relating to use of information in this specification No license express or implied by estoppel or otherwise to any intellectual property rights is granted herein Copyright Intel Corporation 2005 AlertVIEW i960 AnyPoint AppChoice BoardWatch BunnyPeople CablePort Celeron Chip...

Страница 3: ...2 Contents of the Flash 17 2 5 Target Monitors 18 2 5 1 RedHat RedBoot 18 2 6 Host Communications Examples 19 2 6 1 Serial UART Communication 19 2 6 2 JTAG Debug Communication 19 2 6 3 Network Communication 20 2 6 4 GNUPro GDB Insight 21 2 6 4 1 Communicating with RedBoot 21 2 6 4 2 Connecting with GDB 23 3 Hardware Reference Section 25 3 1 Functional Diagram 25 3 2 Board Form Factor Connectivity ...

Страница 4: ...lug Reset Disable Corresponding to Signal Name PBI_AD11 41 3 9 6 4 6 Switch S7A1 6 Hot Plug Capable Disabled Corresponding to Signal Name PBI_AD15 41 3 9 6 4 7 Switch S7A1 7 SMBUS Manageability Address Bit 0 Corresponding to Signal Name PBI_AD17 42 3 9 6 4 8 Switch S7A1 8 SMBUS Manageability Address Bit 3 Corresponding to Signal Name PBI_AD18 42 3 9 6 4 9 Switch S7A1 9 SMBUS Manageability Address ...

Страница 5: ...ng an Executable File From Example Code 61 B 7 Running the Code Lab Debugger 62 B 7 1 Launching and Configuring Debugger 62 B 7 2 Manually Loading and Executing an Application Program 62 B 7 3 Displaying Source Code 63 B 7 4 Using Breakpoints 63 B 7 5 Stepping Through the Code 64 B 7 6 Setting Code Lab Debug Options 64 B 8 Exploring the Code Lab Debug Windows 65 B 8 1 Toolbar Icons 65 B 8 2 Worksp...

Страница 6: ...333 I O Processor Functional Block Diagram 25 6 Board Form Factor 26 7 Intel IQ80333 I O Processor Evaluation Platform Board Peripheral Bus Topology 31 8 Flash Connection on Peripheral Bus 32 9 JTAG Port Pin out 36 10 RESET Sources 37 11 Default Switch Setting Switch S7A1 38 12 Flash Connection to Peripheral Bus 46 13 Intel 80333 I O Processor Memory Map 48 14 Intel 80333 I O Processor Hardware Se...

Страница 7: ...I X Bus B Speed Enable Settings and Operation Mode 41 25 S7A1 5 PCI X Bus B Hot Plug Reset Disable Settings and Operation Mode 41 26 Switch S7A1 6 Hot Plug Capable Disabled Settings and Operation Mode 41 27 Switch S7A1 7 SMBUS Manageability Address Bit 0 Settings and Operation Mode 42 28 Switch S7A1 8 SMBUS Manageability Address Bit 3 Settings and Operation Mode 42 29 Switch S7A1 9 SMBUS Manageabi...

Страница 8: ...y 2005 Customer Reference Board Manual Intel IQ80333 I O Processor Contents Revision History Date Revision Description March 2005 001 Initial Intel Developer Web Site Release http developer intel com design iio ...

Страница 9: ...r Related Documentation List Document Number Intel 80333 I O Processor Developer s Manual 305432 Intel 80333 I O Processor Datasheet 305433 Intel 80333 I O Processor Design Guide 305434 Intel 80333 I O Processor Specification Update 305435 Intel Flash Recovery Utility FRU Reference Manual 274071 IEEE Standard Test Access Port and Boundary Scan Architecture IEEE JTAG 1149 1 1990 http www ieee org P...

Страница 10: ...t com cgi bin morpheus home home jsp pSection LED AudioBuzzer DMT 1206 SMT Manufacturer RDI URL http www rdi electronics com products Audio DMT 1206 SMT html NVSRAM STK14C88 3 N 35 Manufacturer SIMTEK URL http www simtek com product information datasheets 256K PDF STK14C88 3 pdf CPLD XC9572XL 10TQ100C Manufacturer XILINK URL http www xilinx com bvdocs publications ds057 pdf Temperature Sensor LM75...

Страница 11: ...chitecture and the company that licenses it CRB Customer Reference Board ICE In Circuit Emulator A piece of hardware used to mimic all the functions of a microprocessor IOP I O processor JTAG Joint Test Action Group A hardware port supplied on Intel XScale microarchitecture evaluation boards used for in depth testing and debugging PPCI X Primary PCI X PSU Power Supply Unit SPCI X Secondary PCI X ...

Страница 12: ...y Two I2 C Bus Interface Units BIU Two 16550 Compatible UARTs with flow control 4 pins Eight General Purpose Input Output GPIO Ports The 80333 is an integrated processor that addresses the needs of intelligent I O applications and helps reduce intelligent I O system costs PCI Express is an industry standard high performance low latency system interconnect The 80333 PCI Express upstream link is cap...

Страница 13: ...Customer Reference Board Manual 13 Intel IQ80333 I O Processor Introduction Figure 1 Intel 80333 I O Processor Block Diagram 0 1 23 1 23 3 3 ...

Страница 14: ...face Interposer Card may be used for the memory bus Information supplied separately Memory 256 MB 512 Mb x 16 DDRII SDRAM 400 MHz DIMM ECC Registered Onboard Power Board sources 1 25 V 2 5 V 3 3 V 5 V 12 V and 12 V from primary PCI connector All core voltages are derived from 3 3 V supply Auxiliary power for the Secondary PCI slot Power LED Power on green Primary PCI PCI Express x8 lane RAID Suppo...

Страница 15: ...s Be sure you are properly grounded before removing the board from the anti static bag 2 2 1 First Time Installation and Test For first time installation visually inspect the 80333 for any damage made during shipment Follow the host system manufacturer s instructions for installing a PCI Express adapter card The board is a full length host bus adapter card that requires a PCI Express slot free fro...

Страница 16: ... see Section 3 9 4 Connector Summary that is used to power the secondary PCI X slot This connector is compatible with a standard ATX hard drive power connector Caution Before connecting power to the entire system verify that the auxiliary system power to the secondary PCI X slot and the main power to the 80333 are both connected Both power rails should come up at the same time When there is not a ...

Страница 17: ...e The following tools are available for evaluation purposes please contact appropriate vendor These tools are for evaluation purposes and do not include any support Please contact the vendor directly for additional information and support They include but are not limited to RedHat GNUPro tools ARM RealView Developer Suite WindRiver VxWorks RTOS and Tornado Development Tools Wasabi Systems NetBSD O...

Страница 18: ...em s environment It can be used for both product development debug support and for end product deployment Flash and network booting Here are some highlights of RedBoot capabilities Boot scripting support Simple command line interface for RedBoot configuration and management accessible via serial terminal or Ethernet telnet see Section 2 6 4 GNUPro GDB Insight on page 21 Integrated GDB stubs for co...

Страница 19: ...ptop computer but it is not necessary The host computer when loaded with the proper software can communicate with the board 2 6 2 JTAG Debug Communication Using a JTAG Emulator to communicate with the board Figure 3 Please note that the evaluation board is plugged into a host machine as in the figure below You can use an additional laptop computer but it is not necessary The host computer when loa...

Страница 20: ...munication Using a standard network connection the user can communicate with the board via the ethernet port Redboot also allows the user to remotely boot the platform using a BOOTP server through the network Connection Figure 4 Network Communication Example A B C D E F G H S EL EC TE D O N L IN E ...

Страница 21: ...tools can be used Win32 using HyperTerminal UNIX using Kermit Linux using Minicom Solaris using Tip RedBoot Monitor startup Description terminal emulator runs on host and communicates with the board via the serial cable Start Power up the IQ80333 While the reset is asserted the two 7 segment LEDs sequentially display 88 A0 through A6 followed by SL Scrub loop When RedBoot is successfully booted it...

Страница 22: ...ta Bits 8 Parity none Stop Bits 1 Flow Control none Start HyperTerminal Select Call from HyperTerminal panel Reset or power up IQ80333 The Host screen reads For further information on the GDB Insight Debugger refer to the content of the GNUPro CD and or the GNUPro Debugging Tools manual This setup assumes that RedBoot is Flashed on the board RedBoot tm debug environment built dd mm yy Mon dd 2004 ...

Страница 23: ... debug information and symbols GDB set remotebaud 115200 Set baud rate for the 80333 Connect COM port When using Windows command prompt GDB target remote com1 Example screen output from board to host GDB target remote com1 Remote debugging using com1 GDB When using Linux GDB target remote dev ttyS0 GDB load Load the program to the board may have to wait a few seconds GDB break main Set breakpoint ...

Страница 24: ...24 Customer Reference Board Manual Intel IQ80333 I O Processor Getting Started This Page Left Intentionally Blank ...

Страница 25: ...the functional block for the 80333 Figure 5 Intel 80333 I O Processor Functional Block Diagram DDR II 400 GPIOs DDR SDRAM Battery Backup 8 MB StrataFLASH JTAG Slot RS 232 I2C X8 Edge Connector HEX LED Buzzer Local Bus PCI X Bus IOP 100 MHz Slot PCI X Bus Slot 133 MHz Intel 80333 I O Processor PCI Express Gig E RS 232 Target Market ROMB PCI Express RAID card ...

Страница 26: ...as two serial ports and one RJ 45 Ethernet port The 80333 has one JTAG port compliant with ARM Multi ICE 20 pin connector standard The JTAG is targeted for the Intel XScale core and the CPLD and is used for software debug purposes Figure 6 Board Form Factor 107 P C I X S lot s tradd les b oard e dge 312 C P LD B attery Flash B uz zer Pow er Status P erip hera l B us H eade r Intr G P IO H ea der A...

Страница 27: ...Table 7 below The numbers do not include the power required by a PCI X card mounted on the expansion slot Note The maximum current was calculated but not measured This numbers do not include the power required by a PCI X card mounted on the expansion slot s Table 7 Power Features Voltage Rail Maximum Current 3 3 V 6971 mA 5 V 7 mA 12 V 105 mA ...

Страница 28: ...ata is read The IQ80333 features on board registered DDRII 400 MHz SDRAM arranged 512 Mbit x16 in density 256 MB and with ECC 3 4 1 1 Battery Backup Battery backup is provided to save any information in DDR during a power failure The evaluation board contains a 4 V Li ion battery a charging circuit and a regulator circuit DDRII technology provides enabling data preservation through the self refres...

Страница 29: ...al Flash size is 8 MB 80333 Flash technology is based on Intel StrataFlash family 80333 Flash uses a 16 bit interface 80333 Flash utilizes the 80333 Peripheral Bus 80333 May be programmed using the PCI X interface Flash Recovery Utility FRU Utility 80333 May be programmed using a RAM based software target monitor RedHat RedBoot and ARM Firmware Suite 80333 May be programmed using a JTAG emulation ...

Страница 30: ...terrupt Routing to Intel 80333 I O Processor Interrupt System Resource HPI Temperature Sensor Header S_INTA PCI X Slot INTB Header S_INTB PCI X Slot INTC Header S_INTC PCI X Slot INTD Header S_INTD PCI X Slot INTA Header P_INTA PCI X Card Edge INTA Header P_INTB PCI X Card Edge INTB Header P_INTC PCI X Card Edge INTC Header P_INTD PCI X Card Edge INTD Header ...

Страница 31: ...Processor Evaluation Platform Board Peripheral Bus Topology Agilent HDSP A103Hex Display FLASH28F640J3C 16 bit 8Mb RDI DMT 1206 SMT AudioBuzzer XILINX XC9572XL 10TQ100C CPLD Grayhill HAB16W Rotary Switch Intel 80333 I OProcessor PBI Bus SIMTEK STK14C88 3N35 NVSRAM PC104 Connector Table 10 Peripheral Bus Features Description The bus width can be 8 bit or 16 bit and runs at 66 MHz The bus is utilize...

Страница 32: ...le 11 Flash ROM Features Description Flash is an Intel StrataFlash technology Part number 28F640J3C Flash size is 8 MB The connection to the peripheral bus is depicted by Figure 8 Figure 8 Flash Connection on Peripheral Bus Intel 80333 I O Processor CS PCE0 Flash 28F640J3C 16 bit 8 Mb Intel 80333 I O Processor ...

Страница 33: ...s range is from CE86 0000 to CE86 FFFF in hex Please see Section 4 2 2 Peripheral Bus Memory Map on page 47 for more details 3 6 5 HEX Display The two pairs of Agilent HDSP A103 seven segment LEDs are used for displaying POST codes or other software generated debug codes Both HEX displays are individually addressed The left HEX display address range is CE84 0000 to CE84 FFFF in hex The right HEX d...

Страница 34: ...re details on addressing the CPLD Table 13 Battery Status Buffer Requirements BIT Read Write Name Description 0 R Battery Present 0 No backup battery 1 Battery backup is present 1 R Battery Charged 0 Battery is not fully charged 1 Battery is fully charged 2 R Battery Discharged 0 Battery backup is not fully discharged 1 Battery backup is fully discharged 3 R W Battery Enable 0 Disable battery back...

Страница 35: ...3 I O Processor Hardware Reference Section 3 7 Debug Interface 3 7 1 Console Serial Port The platform has two serial ports for debug purposes as described in Section 3 6 Intel IQ80333 I O Processor Evaluation Platform Board Peripheral Bus on page 31 ...

Страница 36: ... Debug The 80333 has a 20 pin JTAG connector J7D2 that is in compliant with ARM Multi ICE guidelines 3 7 2 1 JTAG Port Figure 9 JTAG Port Pin out A9457 01 VTref 1 nTRST 3 TDI 5 TMS 7 TCK 9 RTCK 11 TDO 13 nSRST 15 DBGRQ 17 DBGACK 19 Vsupply 2 GND 4 GND 6 GND 8 GND 10 GND 12 GND 14 GND 16 GND 18 GND 20 ...

Страница 37: ... PCI reset resets all devices on the board It occurs during the power up The SRST signal from the JTAG connector is a bi directional signal that can force a reset similar to the power up reset on the board Figure 10 RESET Sources DDR II SDRAM Intel 80333 I O Processor PCI X Con A PCI X Con B JTAG Con Debounce CPLD A_RST B_RST RST LAN_PWR_GOOD PWRGD TRST SRST Power Delay RESETIN Reset Button 82545E...

Страница 38: ...set S7A1 1 APCI X Bus PCI XBus A Speed Set Closed S7A1 2 IOP RESET Sets IOP Reset Mode operation Open S7A1 3 IOP RETRY Sets IOP RETRY Mode operation Open S7A1 4 BPCI X Bus PCI X Bus B speed set Closed S7A1 5 BPCI X Bus PCI X Bus B Hot Plug Reset Closed S7A1 6 BPCI X Bus Hot Plug Capable Disable Closed S7A1 7 SMBUS Bus SMBUS Manageability address bit 5 Open S7A1 8 SMBUS Bus SMBUS Manageability addr...

Страница 39: ...e Open J9D3 Buzzer Volume Open Table 18 Connector Summary Connector Description J1D1 RJ45 Network Connector for GbE NIC J1E1 RJ11 Dual Serial Port Connector J1L1 J1M1 J1M2 J1N1 J2M1 J2M2 SMA connectors J1R1 Secondary PCI X Expansion bus Slot J2A1 Secondary PCI X Expansion bus Slot J2D1 Power header for fan J2D2 GPIO tap in Header J1B1 J5D1 J5C1 Test headers J2E1 Edge connector for primary PCI Expr...

Страница 40: ...Hz 3 9 6 4 2 S7A1 2 Reset I O Processor Core Corresponding to Signal Name PBI_AD5 RESET MODE is latched at the de asserting edge of P_RST and it determines when the 80333 is held in reset until the Intel XScale core Reset bit is cleared in the PCI Configuration and Status Register Table 20 Rotary Switch Settings Position Description 0 Factory Default Enables private devices on the secondary PCI X ...

Страница 41: ...gnal Name PBI_AD15 This switch allows the user to enable hot plug devices on the secondary PCI X bus B Table 22 Switch S7A1 2 Reset IOP Settings and Operation Mode S7A1 2 Operation Mode Open Don t hold in reset enable IOP core Default mode Closed Hold IOP core in reset Table 23 Switch S7A1 3 RETRY Settings and Operation Mode S7A1 3 Operation Mode Open Configuration Retry Enabled use when booting i...

Страница 42: ...16 This allows 80333 to address SMBus Slave Address 1 PBI_A16 Table 27 Switch S7A1 7 SMBUS Manageability Address Bit 0 Settings and Operation Mode S7A1 6 Operation Mode Open SMBus Manageablity Address Bit 0 1 Default Mode Closed SMBus Manageablity Address Bit 0 0 Table 28 Switch S7A1 8 SMBUS Manageability Address Bit 3 Settings and Operation Mode S7A1 8 Operation Mode Open SMBus Manageablity Addre...

Страница 43: ...t Flash NC 8 bit Flash default mode Table 33 Jumper J1C1 Descriptions Jumper Description Factory Default J1C1 JTAG Chain Enable 1 2 Table 34 Jumper J1C1 Settings and Operation Mode J1C1 Operation Mode Pins 1 2 Enables JTAG Chain for IOP only Default Mode Pins 3 4 Enables JTAG Chain for IOP CPLD Pins 5 6 Enables JTAG Chain for IOP CPLD GBE Pins 7 8 Enables TRST pull down resistor Table 35 Jumper J1...

Страница 44: ... to EEPROM U7B2 Default Mode Pins 3 4 Connects SM_SDTA to EEPROM U7B2 Default Mode Pins 5 6 Connects SM_SCLK to GE_SMCLK for GBE control Pins 7 8 Connects SM_SDTA to GE_SMDAT for GBE control r Pins 9 10 Connects SM_SCLK to PE_SMCLK for PCI E bus control Pins 11 12 Connects SM_SDTA to PE_SM_SDAT for PCI E bus control Table 39 Jumper J9D3 Descriptions Jumper Description Factory Default J9D3 Buzzer V...

Страница 45: ...on 8 table 34 for supported DDR333 and DDR II configurations For all registers relating to DRAM and other MCU related registers see the Intel 80333 I O Processor Developer s Manual 4 2 Components on the Peripheral Bus The 80333 has a peripheral bus which contains the following peripheral devices Flash ROM CPLD Audio Buzzer Rotary Switch Hex Display Peripheral memory Mapped Register Locations and a...

Страница 46: ... 80333 Internal Bus By default address 0x0 is pointing to PCE0 where Flash is located Currently the Intel Flash Recovery Utility FRU can be used with the IQ80333 Another alternative to FRU would be to reprogram the Flash through JTAG or using Redboot commands when Redboot is currently loaded onto the board For more information on using Redboot to program the Flash please see Redboot Manual Figure ...

Страница 47: ...memory re mapped CE80 0000 CE80 FFFF 64 KB 8 bit Product Code CE81 0000 CE81 FFFF 64 KB 8 bit Board Stepping CE82 0000 CE82 FFFF 64 KB 8 bit CPLD Firmware Revision CE83 0000 CE83 FFFF 64 KB 8 bit Discrete LEDs CE84 0000 CE84 FFFF 64 KB 8 bit Hex Display Left CE85 0000 CE85 FFFF 64 KB 8 bit Hex Display Right CE86 0000 CE86 FFFF 64 KB 8 bit Buzzer Control CE87 0000 CE87 FFFF 64 KB 8 bit 32 KB NV RAM...

Страница 48: ...mory space for the 80333 before RedBoot boots Figure 13 Intel 80333 I O Processor Memory Map Peripheral Memory Mapped Registers I O Processor Reserved 0000 0000H ADDRESS FFFF FFFFH Reserved Address Space FFFF E900H FFFF E000H Code Data External Memory ATU Outbound Memory Translation Windows 8000 0000H ATU Outbound Direct Addressing Window 8800 0000H External Memory Code Data External Memory ATU Ou...

Страница 49: ...source code you may also go to the following location on the Intel site http developer intel com design intelxscale dev_tools 021022 index htm Virtual Address Physical Address Size MB Description 0x0000 0000 0x0000 0000 2048 SDRAM 64 bit ECC 0x8000 0000 0x8000 0000 128 ATU Outbound Memory Translation Windows 0x8800 0000 128 Unused 0x9000 0000 0x9000 0000 1 ATU OUtbound I O Translation Window 0x901...

Страница 50: ...le for the scrub ECC initialization code Initialization Sequence 1 Disable interrupts Technically they are disabled at reset but for soft reset this is included 2 Init PBIU Peripheral Bus Interface Unit chip selects 3 Enable I cache 4 Move Flash to 0xF0000000 5 Set TTB and Enable MMU 6 Read DIM for memory parameters 7 Set Memory Parameters 8 Delay 9 Turn DDRAM on 10 Delay 11 Enable Data Cache 12 E...

Страница 51: ...re routed through the XINT pins on the 80333 Please see Table 9 for more details External interrupts are routed through the XINT pins on the 80321 They include INTA INTB form PCI X expansion slot INTA from 82544 GBE and UART interrupt Steering and Status registers are in 80321 see Intel 80321 I O Processor Developer s Manual Timers Internal to 80333 Refer to Intel 80333 I O Processor Developer s M...

Страница 52: ...52 Customer Reference Board Manual Intel IQ80333 I O Processor IQ80321 and IQ80333 Comparisons This Page Left Intentionally Blank ...

Страница 53: ...opment tools and can begin working on new applications B 1 2 Necessary Hardware and Software This example uses the MGC Code Lab plug in for Microsoft Visual Studio the GNU Pro compiler the Macraigor Raven JTAG connector and the 80333 B 1 3 Related Documents Many of these documents load as part of MGC Code Lab install Start Programs Accelerated Technology Documentation This menu contains both the A...

Страница 54: ...Processor Getting Started and Debugger B 1 4 Related Web Sites Macraigor http www ocdemon net http developer intel com design intelxscale dev_tools 021022 index htm http developer intel com design iio http developer intel com design iio papers 273961 htm ...

Страница 55: ...n the Raven can be found at the Macraigor web site Test software for the Raven is free and available for download at http www ocdemon net Merchant2 merchant mv Screen CTGY Store_Code MTS Category_C ode pinouts Connect a serial cable from the evaluation board to the host Note The serial cable connects to the evaluation board with an RJ11 connector and connects to the host computer serial port via a...

Страница 56: ...xe under the program directory Note Do not install over an old version of MGC Code Lab When necessary uninstall Code Lab with Add Remove programs under the Control Panel before reinstalling To view the soft copies of document Adobe Acrobat Reader is needed The latest version can be downloaded at http www adobe com Figure 15 Software Flow Diagram Application Code MGC Code Lab Macraigor DLL Memory F...

Страница 57: ...rner of the Start Page window 5 The new project is now in the Solution Explorer window When this window is not open open it by View Solution Explorer 6 Right click on Project80333 and select Save Project80333 7 From http developer intel com design iio swsup Tester1LED htm download the following zip file Tester1LED from the Software Support section containing the example code files to the newly cre...

Страница 58: ... bold Note that the assembler and the linker are invoked by GCC a Compiler path ToolDir BIN XSCALE ELF GCC EXE b Assembler path ToolDir BIN XSCALE ELF GCC EXE c Linker path ToolDir BIN XSCALE ELF GCC EXE d Librarian path ToolDir BIN XSCALE ELF AR EXE 5 In the left box click on Debugging General When the checkboxes are available in your version set all four debug options to false 6 Click Apply and ...

Страница 59: ...on net Merchant2 merchant mv Screen CTGY Store_Code MTS Categ ory_C ode Software This Flash programmer only supports certain file formats Intel Hex Motorola srec and standard elf executable and linking format RedBoot s19 and RedBoot srec are both srec files Macraigor offers conversion tools to convert existing file types to a supported file type These conversion tools are located at C MGC codelab ...

Страница 60: ...rns to the Connect window 6 Now press Connect Assembly code now visible 7 Select Memory Flash The OCDemon Flash Memory Programmer window appears 8 The Flash programmer needs a file which is architecture specific in this case In the Flash programmer window select File Open then choose the file XscaleIQ80333 ocd at C MGC Embedded codelab codelab Debug Macraigor 9 Click the Program button 10 Click Br...

Страница 61: ... executed This requires that the source code is available and linked by the debugger to the executable code that is running on the evaluation board B 6 Building an Executable File From Example Code 1 Launch Code Lab EDE and open Project80333 2 Select code lab EDE Rebuild Project Note A project can have more than one solution but in this example there is only one solution for the project so there i...

Страница 62: ...toolbar icons Leave the mouse over the debug icons across the top on the toolbar to see a brief explanation of each 4 Click on the go icon and let RedBoot boot takes a minute until the RedBoot prompt RedBoot appears in the Console window click the Console tab at the bottom of the Debug window to view the Console window 5 From the console window a type diag b hit Enter The RedBoot Diagnostic functi...

Страница 63: ...any of these gray circles and a red dot appears The red dot represents a break point Single click the red dot to remove it or click the Remove all breakpoints icon Place a breakpoint on the following lines of code in blink c displayLED leds 8 leds 0 LED display 80 displayLED leds 0 leds 3 LED display 03 displayLED leds 3 leds 2 LED Display 32 displayLED leds 2 leds 1 LED display 21 displayLED leds...

Страница 64: ... line in blink c 8 The animate icon can also be used to provide a Step Into effect that occurs at a specified time interval default of 1 second This can be modified in the Settings section of the View Options menu Experiment with this as desired 9 Use Halt to stop the animate mode before the next breakpoint 10 Also note that Go can be pressed at any time to continue execution from the current line...

Страница 65: ...not be able to find the file B 8 3 Source Code The source code windows are opened by double clicking on the source files in the Workspace window under the files tab Viewing of mixed Assembly and C code or C code only is controlled by the tabs at the bottom of these windows B 8 4 4 Debug and Console Windows The Debug window displays debugger activity messages while the Debug tab is displayed Script...

Страница 66: ...lecting Go To Memory Notice how the Memory window is brought up and the address contained in that register is shown Click on the registers tab Red means that the register value changed since the last fetch as opposed to black which represents no change Register values can be manually changed in this window B 8 7 Watch Window It is often useful during the debugging process to keep an eye on a few s...

Страница 67: ... constraints B 9 2 Hardware and Software Breakpoints The following section provides a brief overview of breakpoints See the Intel 80333 I O Processor Developer s Manual for more detailed information B 9 2 1 Software Breakpoints Software breakpoints are setup and utilized via debugger utilities such as Code Lab The abilities of software breakpoints were seen in Section B 7 of this Guide Program exe...

Страница 68: ...tion to a debug event handling routine The Intel 80200 processor debug architecture defines the following debug exceptions instruction breakpoint data breakpoint software breakpoint external debug break exception vector trap trace buffer full break When a debug exception occurs the processor actions depend on whether the debug unit is configured for Halt mode or Monitor mode ...

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