Table 11. MRC Progress Codes
Progress Code
Main Sequence
Subsequences/Subfunctions
0xB0
Detect DIMM population
—n/a—
0xB1
Set DDR4 frequency
—n/a—
0xB2
Gather remaining SPD data
—n/a—
0xB3
Program registers on the memory controller level
—n/a—
0xB4
Evaluate RAS modes and save rank information
—n/a—
0xB5
Program registers on the channel level
—n/a—
0xB6
Perform the JEDEC defined initialization
sequence
—n/a—
0xB7
Train DDR4 ranks
—n/a—
0x01
Read DQ/DQS training
0x02
Receive Enable training
0x03
Write Leveling training
0x04
Write DQ/DQS training
0x05
DDR channel training done
0xB8
Initialize CLTT/OLTT
—n/a—
0xB9
Hardware memory test and init
—n/a—
0xBA
Execute software memory init
—n/a—
0xBB
Program memory map and interleaving
—n/a—
0xBC
Program RAS configuration
—n/a—
0xBF
MRC is done
—n/a—
Содержание HNS7200AP
Страница 2: ... This page is intentionally left blank ...
Страница 16: ......
Страница 52: ...Figure 47 Install LACC brackets 2 Figure 48 Install LACC brackets 3 ...
Страница 53: ...7 Connect the pump cable to the 4 pin CPU Fan Header J6J2 Figure 49 Connect the Pump Cable fan header J6J2 ...
Страница 66: ...Figure 71 Fabric Processor and IFT Cable Connections ...