Intel GD82559ER, Техническое описание

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GD82559ER — Networking Silicon
iv Datasheet
6.1.2 100BASE-TX Transmit Blocks ......................................................................... 37
6.1.3 100BASE-TX Receive Blocks .......................................................................... 40
6.1.4 100BASE-TX Collision Detection ..................................................................... 41
6.1.5 100BASE-TX Link Integrity and Auto-Negotiation Solution.............................. 41
6.1.6 Auto 10/100 Mbps Speed Selection ................................................................. 41
6.2 10BASE-T Functionality ................................................................................................... 41
6.2.1 10BASE-T Transmit Clock Generation............................................................. 41
6.2.2 10BASE-T Transmit Blocks.............................................................................. 42
6.2.3 10BASE-T Receive Blocks............................................................................... 42
6.2.4 10BASE-T Collision Detection.......................................................................... 43
6.2.5 10BASE-T Link Integrity ................................................................................... 43
6.2.6 10BASE-T Jabber Control Function ................................................................. 43
6.2.7 10BASE-T Full Duplex ..................................................................................... 43
6.3 Auto-Negotiation Functionality.......................................................................................... 43
6.3.1 Description ....................................................................................................... 44
6.3.2 Parallel Detect and Auto-Negotiation ............................................................... 44
6.4 LED Description................................................................................................................ 45
7. PCI CONFIGURATION REGISTERS ........................................................................................... 47
7.1 LAN (Ethernet) PCI Configuration Space ......................................................................... 47
7.1.1 PCI Vendor ID and Device ID Registers .......................................................... 47
7.1.2 PCI Command Register ................................................................................... 48
7.1.3 PCI Status Register.......................................................................................... 49
7.1.4 PCI Revision ID Register.................................................................................. 50
7.1.5 PCI Class Code Register ................................................................................. 50
7.1.6 PCI Cache Line Size Register.......................................................................... 50
7.1.7 PCI Latency Timer............................................................................................ 51
7.1.8 PCI Header Type.............................................................................................. 51
7.1.9 PCI Base Address Registers............................................................................ 51
7.1.10 PCI Subsystem Vendor ID and Subsystem ID Registers ................................. 53
7.1.11 Capability Pointer ............................................................................................. 53
7.1.12 Interrupt Line Register...................................................................................... 53
7.1.13 Interrupt Pin Register ....................................................................................... 54
7.1.14 Minimum Grant Register .................................................................................. 54
7.1.15 Maximum Latency Register.............................................................................. 54
7.1.16 Capability ID Register....................................................................................... 54
7.1.17 Next Item Pointer.............................................................................................. 54
7.1.18 Power Management Capabilities Register ....................................................... 54
7.1.19 Power Management Control/Status Register (PMCSR)................................... 55
7.1.20 Data Register ................................................................................................... 56
8. CONTROL/STATUS REGISTERS................................................................................................ 57
8.1 LAN (Ethernet) Control/Status Registers.......................................................................... 57
8.1.1 System Control Block Status Word .................................................................. 58
8.1.2 System Control Block Command Word ............................................................ 59
8.1.3 System Control Block General Pointer............................................................. 59
8.1.4 PORT ............................................................................................................... 59
8.1.5 Flash Control Register...................................................................................... 59
8.1.6 EEPROM Control Register............................................................................... 59
8.1.7 Management Data Interface Control Register.................................................. 59
8.1.8 Receive Direct Memory Access Byte Count..................................................... 60
8.1.9 Early Receive Interrupt..................................................................................... 60