Intel BX80619I73960X, Техническое описание

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Datasheet, Volume 1 37
Power Management
4.2.6 Package C-State Power Specifications
Table 4-9 lists the processor package C-state power specifications for various processor
SKUs.
The C-state power specification is based on post-silicon validation results. The
processor case temperature is assumed at 50 °C for all C-states.
4.3 System Memory Power Management
The DDR3 power states can be summarized as the following:
• Normal operation (highest power consumption)
• CKE Power-Down: Opportunistic, per rank control after idle time. There may be
different levels.
— Active Power-Down
— Precharge Power-Down with Fast Exit
— Precharge power Down with Slow Exit
• Self Refresh: In this mode no transaction is executed. The DDR consumes the
minimum possible power.
4.3.1 CKE Power-Down
The CKE input land is used to enter and exit different power-down modes. The memory
controller has a configurable activity timeout for each rank. When no reads are present
to a given rank for the configured interval, the memory controller will transition the
rank to power-down mode.
The memory controller transitions the DRAM to power-down by de-asserting CKE and
driving a NOP command. The memory controller will tri-state all DDR interface lands
except CKE (de-asserted) and ODT while in power-down. The memory controller will
transition the DRAM out of power-down state by synchronously asserting CKE and
driving a NOP command.
When CKE is off, the internal DDR clock is disabled and the DDR power is significantly
reduced.
The DDR defines three levels of power-down:
• Active power-down: This mode is entered if there are open pages when CKE is de-
asserted. In this mode the open pages are retained. Existing this mode is 3–5 DCLK
cycles.
• Precharge power-down fast exit: This mode is entered if all banks in DDR are
precharged when de-asserting CKE. Existing this mode is 3–5 DCLK cycles. The
difference from the active power-down mode is that when waking up, all page-
buffers are empty.
• Precharge power-down slow exit: In this mode the data-in DLLs on DDR are off.
Existing this mode is 3–5 DCLK cycles until the first command is allowed, but about
16 cycles until first data is allowed.
Table 4-9. Package C-State Power Specifications
TDP SKUs C1E (W) C3 (W) C6 (W)
6-Core
130 W (6-core) 53 35 21
4-Core
130 W (4-core) 53 28 16