Intel BLKD955XCSLKR, Технические характеристики продукции, Страница: 16 / 92

Intel Desktop Board D955XCS Technical Product Specification
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1.4 System Memory
The board has four DIMM sockets and supports the following memory features:
•
1.8 V and 1.9 V DDR2 SDRAM DIMMs
•
Unbuffered, single-sided or double-sided DIMMs with the following restriction:
Double-sided DIMMS with x16 organization are not supported.
•
8 GB maximum total system memory. Refer to Section 2.1.1 on page 43 for information on the
total amount of addressable memory.
•
Minimum total system memory: 128 MB
•
ECC DIMMs and non-ECC DIMMs
•
Serial Presence Detect
•
DDR2 667 and 533 MHz SDRAM DIMMs
NOTES
To be fully compliant with all applicable DDR SDRAM memory specifications, the board should be
populated with DIMMs that support the Serial Presence Detect (SPD) data structure. This allows
the BIOS to read the SPD data and program the chipset to accurately configure memory settings
for optimum performance. If non-SPD memory is installed, the BIOS will attempt to correctly
configure the memory settings, but performance and reliability may be impacted or the DIMMs
may not function under the determined frequency.
Table 4 lists the supported DIMM configurations.
Table 4. Supported Memory Configurations
DIMM
Capacity Configuration
(Note 1)
SDRAM
Density SDRAM Organization
Front-side/Back-side Number of SDRAM
Devices
(Note 2)
128 MB SS 256 Mbit 16 M x 16/empty 4 [5]
256 MB SS 256 Mbit 32 M x 8/empty 8 [9]
256 MB SS 512 Mbit 32 M x 16/empty 4 [5]
512 MB DS 256 Mbit 32 M x 8/32 M x 8 16 [18]
512 MB SS 512 Mbit 64 M x 8/empty 8 [9]
512 MB SS 1 Gbit 64 M x 16/empty 4 [5]
1024 MB DS 512 Mbit 64 M x 8/64 M x 8 16 [18]
1024 MB SS 1 Gbit 128 M x 8/empty 8 [9]
2048 MB DS 1 Gbit 128 M x 8/128 M x 8 16 [18]
Notes:
1. In the second column, “DS” refers to double-sided memory modules (containing two rows of SDRAM) and “SS” refers to
single-sided memory modules (containing one row of SDRAM).
2. In the fifth column, the number in brackets specifies the number of SDRAM devices on an ECC DIMM.
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INTEGRATOR’S NOTE
Refer to Section 2.1.1, on page 43 for additional information on available memory.