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Schematic Signal Name FPGA Pin Number

I/O Standard

Description

DDR4_COMP_ODT

1.2 V HS LVCMOS

DDR4 Component On Die Termination

DDR4_COMP_ACT_N

P12

1.2 V HS LVCMOS

DDR4 Component Activate

DDR4_COMP_CS_N

R11

1.2 V HS LVCMOS

DDR4 Component Chip Select

DDR4_COMP_RESET_N

M12

1.2 V HS LVCMOS

DDR4 Component Reset

DDR4_COMP_BG1

L11

1.2 V HS LVCMOS

DDR4 Component Bank Group 1

A.5.8. HPS I/O48 Interface

An HPS I/O48 daughter card is pre-installed with each development kit board.

The Intel Agilex FPGA (two F-tiles) development board connects the 48 HPS I/Os
(

HPS_IOA[24:1]

and

HPS_IOB[24:1]

) to a mezzanine connector for installing the

Intel HPS I/O48 daughter card. This daughter card provides the HPS with USB, UART,

Ethernet, SD card, I

C, and JTAG accessibility.

Table 36.

HPS Pin Assignments

Schematic Signal Name

FPGA Pin Number

I/O Standard

Description

HPS_GPIO0

AC15

1.8 V LVCMOS

USB Clock

HPS_GPIO1

AL15

1.8 V LVCMOS

USB STP

HPS_GPIO2

AJ11

1.8 V LVCMOS

USB DIR

HPS_GPIO3

AM16

1.8 V LVCMOS

USB Data 0

HPS_GPIO4

AH12

1.8 V LVCMOS

USB Data 1

HPS_GPIO5

AN15

1.8 V LVCMOS

USB NXT

HPS_GPIO6

AG13

1.8 V LVCMOS

USB Data 2

HPS_GPIO7

AP16

1.8 V LVCMOS

USB Data 3

HPS_GPIO8

AF14

1.8 V LVCMOS

USB Data 4

HPS_GPIO9

AT16

1.8 V LVCMOS

USB Data 5

HPS_GPIO10

AH10

1.8 V LVCMOS

USB Data 6

HPS_GPIO11

AU15

1.8 V LVCMOS

USB Data 7

HPS_GPIO12

AJ7

1.8 V LVCMOS

Ethernet TX Clock

HPS_GPIO13

AL13

1.8 V LVCMOS

Ethernet TX Enable

HPS_GPIO14

AH8

1.8 V LVCMOS

Ethernet RX Clock

HPS_GPIO15

AM14

1.8 V LVCMOS

Ethernet RX Data Valid

HPS_GPIO16

AD14

1.8 V LVCMOS

Ethernet TX Data 0

HPS_GPIO17

AN13

1.8 V LVCMOS

Ethernet TX Data 1

HPS_GPIO18

AG11

1.8 V LVCMOS

Ethernet RX Data 0

HPS_GPIO19

AP14

1.8 V LVCMOS

Ethernet RX Data 1

HPS_GPIO20

AG9

1.8 V LVCMOS

Ethernet TX Data 2

HPS_GPIO21

AT14

1.8 V LVCMOS

Ethernet TX Data 3

continued...

A. Development Kit Components

739942 | 2022.09.21

Intel

Agilex

™

F-Series FPGA (Two F-Tiles) Development Kit User Guide

Send Feedback

Содержание Agilex F Series

Страница 1: ...Intel Agilex F Series FPGA Two F Tiles Development Kit User Guide Online Version Send Feedback ID 739942 Version 2022 09 21...

Страница 2: ...he Sys Info Tab 17 4 2 4 The GPIO Tab 18 4 2 5 The XCVR Tab 19 4 2 6 The Memory Tab 23 4 3 Control On Board Clock through Clock Controller GUI 25 4 4 Monitor On Board Power Regulator through Power Mon...

Страница 3: ...DR4 DIMM1 Interface 48 A 5 6 DDR4 DIMM2 Interface 52 A 5 7 DDR4 Component Interface 57 A 5 8 HPS I O48 Interface 60 A 6 I2C 61 A 7 Intel MAX 10 SPI Bus 63 A 8 Clock Circuits 63 A 9 HPS Daughter Card 6...

Страница 4: ...I I2C I2C I2C Nios Flash Clock Circuitry IEEE1588 Support Board PWR Circuitry PWR Input uUSB DDR4 x72 DIMM DDR T 1 rank up to 3 200 Mbps DDR4 x72 DIMM DDR T 1 rank up to 3 200 Mbps IO48 Daughter Card...

Страница 5: ...pporting Gen 4 end point connected to a PCIe x16 edge connector gold edge fingers 1x QSFP optical module interface connected to F tile transceiver 1x QSFPDD optical module interface connected to F til...

Страница 6: ...ughter board USB 2 0 MicroUSB cable 240W power adapter and NA EU JP UK cords 1 4 Recommended Operating Conditions Table 2 Recommended Operating Conditions Operating Condition Range of Values Ambient o...

Страница 7: ...Getting Started 2 2 Design Examples Unzip the install package which includes board design files documents and examples directories The table below lists the file directory names and a description of t...

Страница 8: ...nments management Design Examples Memory XCVR GPIO PCIe Gen 4 factory_recovery Contains the original data programmed onto the board before shipment Use this data to restore the board with its original...

Страница 9: ...SW3 3 BMC JTAG selection ON selects the on board blaster as JTAG master when no external blaster is plugged OFF selects the PCIe RP as JTAG master when no external blaster is plugged Default JTAG cha...

Страница 10: ...evelopment kit is designed to operate in two modes As a PCIe Add In Card When operating the card as a PCIe system insert the card into an available PCIe slot and connect a 2x4 pin PCIe power cable fro...

Страница 11: ...or use Since the default configuration mode is Avalon ST x4 the FPGA automatically downloads its configuration image from the QSPI flash device connected to the FPGA s SDM interface When the configura...

Страница 12: ...download and install Java runtime including OpenJDK and OpenJFX on your systems and set up the running environment This is a one time procedure so if you have already completed it before you do not n...

Страница 13: ...download the OpenJFX follow these steps 1 Download the OpenJFX using this link https gluonhq com products javafx 2 Select JavaFX version 17 0 2 3 For the Windows system download the JavaFX Windows x64...

Страница 14: ...ap Logic Analyzer Ensure closing other applications before you use the BTS because the BTS is designed based on the Intel Quartus Prime software The BTS relies on the Intel Quartus Prime software s sp...

Страница 15: ...double click the bat files to run BTS Clock Controller or Power Monitor GUI Figure 6 Windows Console 2 On Linux system you need to run the shell script with root privilege 4 Board Test System 739942...

Страница 16: ...n the Intel Quartus Prime version and the JTAG clock System Connected Disconnected Shows if the board is connected to the system The green sign turns gray if the board becomes disconnected Intel Quart...

Страница 17: ...tion finishes the design begins running in the FPGA The corresponding GUI application tabs that interface with the design are now enabled If you use the Intel Quartus Prime Programmer for configuratio...

Страница 18: ...JTAG chain control shows all the devices currently in the JTAG chain Note Both System Intel MAX 10 and FPGA must be in the JTAG chain when running the BTS GUI 4 2 4 The GPIO Tab The GPIO tab allows yo...

Страница 19: ...to run transceiver tests on your board You can run the test using either electrical loopback modules or optical fiber modules 4 2 5 1 The QSFP NRZ Tab Figure 11 The QSFP NRZ Tab The following sections...

Страница 20: ...ount of pre emphasis on the second pre tap of the transmitter buffer Post tap 1 Specifies the amount of pre emphasis on the post tap of the transmitter buffer Figure 12 QSFP NRZ PMA Setting Data Type...

Страница 21: ...the button Insert Error is only enabled during transaction performance analysis Clear Resets the Detected Errors counter and Inserted Errors counter to zeros Run Control TX and RX performance bars Sh...

Страница 22: ...ontrol functions with the QSFP NRZ tab Figure 15 The QSFPDD NRZ Tab 4 2 5 4 The QSFPDD PAM4 Tab Similar control functions with the QSFP NRZ tab 4 Board Test System 739942 2022 09 21 Intel Agilex F Ser...

Страница 23: ...d the design through BTS Configure Figure 17 The RDIMM1 Tab The following sections describe controls on this tab Start Initiates DDR4 memory transaction performance analysis Stop Terminates transactio...

Страница 24: ...s to test Test Mode Infinite Read and Write default Single Read and Write Test Pattern PRBS default User Defined Constant Walking 0 Walking 1 Error Control This control displays data errors detected d...

Страница 25: ...or Power Monitor GUI is running at the same time Figure 19 ZL30733 The output frequency of ZL30733 is from 0 5 Hz to 750 MHz It can generate up to 10 differential outputs with a total of 5 output fre...

Страница 26: ...ation on the board It also collects temperature from FPGA die power modules and diodes assembled on PCB The Power Monitor GUI communicates with system Intel MAX 10 through a 10 pin JTAG header J3 or U...

Страница 27: ...lt before you can use the board If one or more BTS test items fail it implies either a wrong hardware setting or hardware fault on specific interface 4 6 Identify Test Pass or Fail based on BTS GUI Te...

Страница 28: ...manage configuration download After power on the Intel MAX 10 reads the configuration bitstream programmed into the QSPI flash U4 and sends this data to FPGA SDM interface to program the FPGA The U4 i...

Страница 29: ...Installed Installed Image 0 Default Image 1 Open Installed Image 1 Image 2 Installed Open Image 2 Image 3 Open Open Image 3 5 Development Kits Hardware and Configuration 739942 2022 09 21 Send Feedba...

Страница 30: ...SDM_IO16 set_global_assignment name USE_INIT_DONE SDM_IO13 set_global_assignment name USE_CVP_CONFDONE SDM_IO14 set_global_assignment name USE_NCATTRIP SDM_IO12 set_global_assignment name USE_HPS_COL...

Страница 31: ...ent specifications in accordance with Intel s standard warranty but reserves the right to make changes to any products and services at any time without notice Intel assumes no responsibility or liabil...

Страница 32: ...ex FPGA AGFB027R24C2E2V 2 692 760 Logic Elements LE 912 800 Adaptive Logic Elements ALM 13 272 M20K Blocks 45 640 MLABs 8 528 DSP Blocks 17 056 18x19 Multipliers 744 GPIOs 372 LVDS continued 739942 20...

Страница 33: ...SW6 Intel MAX 10 JTAGEN switch Enables Intel MAX 10 to use the JTAG pins as I Os S1 CPU RESETn Sends an active low signal to the FPGA and Intel MAX 10 which can be used as the RESET for internal desig...

Страница 34: ...al 100 MHz PCIe to U27 Out 2 100 MHz CXL PCIe root port clock to CXL connector J9 U26 Out 0 100 MHz PCIe Bank 13A CH5 Out 1 100 MHz PCIe Bank 13A CH2 U27 Out 0 100 MHz PCIe Bank 12C CH0 Out 1 100 MHz...

Страница 35: ...45B device Input power conditioner for 12V_PCIe U54 MAX16545B device Input power conditioner for 12V_AUX U94 Analog devices LTM4625 5V DC DC voltage regulator U56 Intersil ISL80101 2 5V LDO voltage re...

Страница 36: ...FPGA Configuration You can use the Intel Quartus Prime Programmer to configure the FPGA with your SRAM Object File sof Ensure the following The Intel Quartus Prime Programmer and the Intel FPGA Downl...

Страница 37: ...HY CY7C68013A MAX 10 10M50DAF256 Intel Agilex FPGA USB Data JTAG A 2 2 Programming the FPGA over an External Intel FPGA Download Cable II The figure below shows the high level conceptual block diagram...

Страница 38: ...W2 USB MAX JTAG SEL ON for on board Intel FPGA Download Cable II ON OFF for external Intel FPGA Download Cable II Table 19 SW3 4 position DIP for Configuration Mode Selection and JTAG Control By defau...

Страница 39: ...ard OFF Table 23 SW6 Single DIP for Intel MAX 10 JTAG Enable Switch position Board Label Function Default Position SW6 Intel MAX 10 JTAG Enable ON to share Intel MAX 10 JTAG Pins OFF Table 24 S 1 4 6...

Страница 40: ...n 3 3V S3 PCIE_PERSTn 1 8V S4 GFX_2ND_PERSTn 1 8V S6 CXL_PERSTn 3 3V A 4 2 Switches The Intel Agilex FPGA two F tiles development board includes user controlled switches for selecting various features...

Страница 41: ..._3V3_LED2 1 2V D11 FPGA_3V3_LED3 1 2V D12 FPGA_1V8_CONF_DONE 1 8V D24 CFG_IMAGE0 3 3V D25 CFG_IMAGE1 3 3V A 5 Components and Interfaces This section describes the development board s communication por...

Страница 42: ...N signal is a 100 MHz differential input that is driven from the PC motherboard onto this board through the edge connector This signal connects directly to a Intel Agilex FPGA REFCLK input pin pair us...

Страница 43: ...1 1 4 V PCML Receive bus B23 PCIE_EP_TX_P2 AN1 1 4 V PCML Receive bus B27 PCIE_EP_TX_P3 AU1 1 4 V PCML Receive bus B33 PCIE_EP_TX_P4 BA1 1 4 V PCML Receive bus B37 PCIE_EP_TX_P5 BE1 1 4 V PCML Receive...

Страница 44: ...A43 PCIE_EP_RX_P6 BB4 1 4 V PCML Transmit bus A47 PCIE_EP_RX_P7 BF4 1 4 V PCML Transmit bus A52 PCIE_EP_RX_P8 BK4 1 4 V PCML Transmit bus A56 PCIE_EP_RX_P9 BP4 1 4 V PCML Transmit bus A60 PCIE_EP_RX_...

Страница 45: ...ifferential Signaling QSFPDD Transmit Channel 7 negative QSFPDD_RX0_P AR55 True Differential Signaling QSFPDD Receive Channel 0 Positive QSFPDD_RX0_N AT54 True Differential Signaling QSFPDD Receive Ch...

Страница 46: ...ve QSFP_TX1_N BA51 True Differential Signaling QSFP Transmit Channel 1 negative QSFP_TX2_P BJ51 True Differential Signaling QSFP Transmit Channel 2 Positive QSFP_TX2_N BK52 True Differential Signaling...

Страница 47: ...e CXL_TX_P3 BP52 True Differential Signaling CXL Transmit Channel 3 Positive CXL_TX_N3 BN51 True Differential Signaling CXL Transmit Channel 3 Negative CXL_RX_P0 CC55 True Differential Signaling CXL R...

Страница 48: ...1 DQ6 data DDR4_DIMM1_DQ7 DD26 1 2 V HS LVCMOS DDR4 DIMM1 DQ7 data DDR4_DIMM1_DQS_P0 DD28 1 2 V HS LVCMOS DDR4 DIMM1 Data Strobe Positive for byte lane 0 DDR4_DIMM1_DQS_N0 DC29 1 2 V HS LVCMOS DDR4 DI...

Страница 49: ...yte lane 2 DDR4_DIMM1_DQ24 DE15 1 2 V HS LVCMOS DDR4 DIMM1 DQ24 data DDR4_DIMM1_DQ25 DF14 1 2 V HS LVCMOS DDR4 DIMM1 DQ25 data DDR4_DIMM1_DQ26 DJ15 1 2 V HS LVCMOS DDR4 DIMM1 DQ26 data DDR4_DIMM1_DQ27...

Страница 50: ...R4 DIMM1 DQ47 data DDR4_DIMM1_DQS_P5 DD16 1 2 V HS LVCMOS DDR4 DIMM1 Data Strobe Positive for byte lane 5 DDR4_DIMM1_DQS_N5 DC17 1 2 V HS LVCMOS DDR4 DIMM1 Data Strobe Negative for byte lane 5 DDR4_DI...

Страница 51: ...DDR4_DIMM1_DQ66 CT22 1 2 V HS LVCMOS DDR4 DIMM1 DQ66 data DDR4_DIMM1_DQ67 CR23 1 2 V HS LVCMOS DDR4 DIMM1 DQ67 data DDR4_DIMM1_DQ68 CR19 1 2 V HS LVCMOS DDR4 DIMM1 DQ68 data DDR4_DIMM1_DQ69 CV18 1 2...

Страница 52: ...CL31 1 2 V HS LVCMOS DDR4 DIMM1 Parity DDR4_DIMM1_CS_N1 CK30 1 2 V HS LVCMOS DDR4 DIMM1 Chip Select 1 DDR4_DIMM1_CK_N0 CN31 1 2 V HS LVCMOS DDR4 DIMM1 Clock 0 Positive DDR4_DIMM1_CK_P0 CP30 1 2 V HS L...

Страница 53: ...1 2 V HS LVCMOS DDR4 DIMM2 DQ10 data DDR4_DIMM2_DQ11 CY44 1 2 V HS LVCMOS DDR4 DIMM2 DQ11 data DDR4_DIMM2_DQ12 DA49 1 2 V HS LVCMOS DDR4 DIMM2 DQ12 data DDR4_DIMM2_DQ13 CY48 1 2 V HS LVCMOS DDR4 DIMM...

Страница 54: ...V HS LVCMOS DDR4 DIMM2 Data Strobe Negative for byte lane 3 DDR4_DIMM2_DBI_N3 CT44 1 2 V HS LVCMOS DDR4 DIMM2 Data Bus Inversion for byte lane 3 DDR4_DIMM2_TDQS_N12 CR45 1 2 V HS LVCMOS DDR4 DIMM2 Ter...

Страница 55: ...a DDR4_DIMM2_DQ52 CK36 1 2 V HS LVCMOS DDR4 DIMM2 DQ52 data DDR4_DIMM2_DQ53 CN37 1 2 V HS LVCMOS DDR4 DIMM2 DQ53 data DDR4_DIMM2_DQ54 CL37 1 2 V HS LVCMOS DDR4 DIMM2 DQ54 data DDR4_DIMM2_DQ55 CP36 1 2...

Страница 56: ...or byte lane 8 DDR4_DIMM2_TDQS_N17 CR39 1 2 V HS LVCMOS DDR4 DIMM2 Termination Data Strobe for byte lane 8 DDR4_DIMM2_C1 DJ33 1 2 V HS LVCMOS DDR4 DIMM2 Stacked Device Chip ID 1 DDR4_DIMM2_C0 DH32 1 2...

Страница 57: ...CS_N0 CY42 1 2 V HS LVCMOS DDR4 DIMM2 Chip Select 0 DDR4_DIMM2_RESET_N DC43 1 2 V HS LVCMOS DDR4 DIMM2 Reset DDR4_DIMM2_BG1 DD42 1 2 V HS LVCMOS DDR4 DIMM2 Bank Group 1 A 5 7 DDR4 Component Interface...

Страница 58: ...MP_DQ20 D10 1 2 V HS LVCMOS DDR4 component DQ20 data DDR4_COMP_DQ21 C5 1 2 V HS LVCMOS DDR4 component DQ21 data DDR4_COMP_DQ22 B10 1 2 V HS LVCMOS DDR4 component DQ22 data DDR4_COMP_DQ23 E5 1 2 V HS L...

Страница 59: ...onent Address 15 DDR4_COMP_A14 T4 1 2 V HS LVCMOS DDR4 Component Address 14 DDR4_COMP_A13 U3 1 2 V HS LVCMOS DDR4 Component Address 13 DDR4_COMP_A12 Y6 1 2 V HS LVCMOS DDR4 Component Address 12 DDR4_C...

Страница 60: ...V LVCMOS USB Clock HPS_GPIO1 AL15 1 8 V LVCMOS USB STP HPS_GPIO2 AJ11 1 8 V LVCMOS USB DIR HPS_GPIO3 AM16 1 8 V LVCMOS USB Data 0 HPS_GPIO4 AH12 1 8 V LVCMOS USB Data 1 HPS_GPIO5 AN15 1 8 V LVCMOS US...

Страница 61: ...CMOS SD Card Clock HPS_GPIO39 AP10 1 8 V LVCMOS SD Card Data 1 HPS_GPIO40 AC9 1 8 V LVCMOS SD Card Data 2 HPS_GPIO41 AM10 1 8 V LVCMOS SD Card Data 3 HPS_GPIO42 AB10 1 8 V LVCMOS OSC Clock HPS_GPIO43...

Страница 62: ...able 37 Intel MAX 10 I2C Signals Schematic Signal Name MAX Pin Number I O Standard Description MAX_I2C_SCL J11 3 3 V open drain Intel MAX 10 I2C clock MAX_I2C_SDA J12 3 3 V open drain Intel MAX 10 I2C...

Страница 63: ...z Y1 OSC 125 MHz PPS_FPGA_clkout ToD_master_clk_125M_P N 125 MHz clk_FPGA_100M_P N 100 MHz PTP_sample_clk_250M_P N 250 MHz DDR4_DIMM1_refclk_P N 166 625 MHz DDR4_DIMM2_refclk_P N 166 625 MHz DDR4_comp...

Страница 64: ...lock CIPRI_LOW_REFCLK_P N 153 6 Mhz Differential AR49 AU49 CIPRI low clock U27 REFCLK_CXL_CONN_P N 100 Mhz HCSL BG49 BF48 PCIe REFCLK bank 12C channel 1 REFCLK_CXL_EP_P N 100 Mhz HCSL BC49 BE49 PCIe R...

Страница 65: ...CMOS USB DATA4 HPS_GPIO9 AT16 1 8 V LVCMOS USB DATA5 HPS_GPIO10 AH10 1 8 V LVCMOS USB DATA6 HPS_GPIO11 AU15 1 8 V LVCMOS USB DATA7 HPS_GPIO12 AJ7 1 8 V LVCMOS Ethernet TX clock HPS_GPIO13 AL13 1 8 V L...

Страница 66: ...S SDMMC CMD HPS_GPIO38 AD8 1 8 V LVCMOS SDMMC clock HPS_GPIO39 AP10 1 8 V LVCMOS SDMMC Data1 HPS_GPIO40 AC9 1 8 V LVCMOS SDMMC Data2 HPS_GPIO41 AM10 1 8 V LVCMOS SDMMC Data3 HPS_GPIO42 AB10 1 8 V LVCM...

Страница 67: ...iliary power connections the board will not power on when installed in a PCIe system The power switch SW5 is ignored when the board is used in the PCIe system Figure 28 In a Standard PCIe Compliant Sy...

Страница 68: ...01 ISL80101 TPS2557 I_Limit TPS3557 I_Limit ISL80101 MAX16545 FB FB FB LDO ISL80101 VCCIO_SDM VCCIO_HPS VCCBAT VCCFUSEWR_SDM VCCH_SDM VCC_HSSI_GXF VCCL_SDM VCCH VCC VCCP VCCL_HPS VCCPLLDIG_HPS VCCPLLD...

Страница 69: ...e up to a maximum power consumption of 150 W under this environment Two MAX31730 3 channel remote temperature sensor devices are connected to the Intel Agilex FPGA s internal temperature diodes The fu...

Страница 70: ...tle 47 the operator of the kit must operate under the authority of an FCC licenseholder or must secure an experimental authorization under Part 5 of the United States CFR Title 47 Safety Assessment an...

Страница 71: ...all DC power from the board system The socket outlet must be installed near the equipment and must be readily accessible System Grounding Earthing To avoid shock you must ensure that the power cord is...

Страница 72: ...e of this product during an electrical storm Risk of Fire To reduce the risk of fire keep all flammable materials a safe distance away from the boards and power supply You must configure the developme...

Страница 73: ...ference to radio communications If this equipment does cause harmful interference to radio or television reception which can be determined by turning the equipment on and off you are required to take...

Страница 74: ...of fire explosion or chemical burn if the battery is mistreated punctured or crushed Do not attempt to disassemble Do not incinerate Observe proper polarity when replacing battery Do not dispose the...

Страница 75: ...ds mandated by Directive 2014 30 EU Because of the nature of programmable logic devices it is possible for the user to modify the development kit in such a way as to generate electromagnetic interfere...

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