MCHBAR
Registers
R
Intel
®
82925X/82925XE MCH Datasheet
89
Bit
Access &
Default
Description
6:4 R/W
000 b
Mode Select (SMS).
These bits select the special operational mode of the DRAM
interface. The special modes are intended for initialization at power up.
000 = Post Reset state – When the MCH exits reset (power-up or otherwise), the
mode select field is cleared to “000”.
During any reset sequence, while power is applied and reset is active, the
MCH de-asserts all CKE signals. After internal reset is de-asserted, CKE
signals remain de-asserted until this field is written to a value different
than “000”. On this event, all CKE signals are asserted.
During suspend, MCH internal signal triggers DRAM controller to flush
pending commands and enter all ranks into Self-Refresh mode. As part of
resume sequence, MCH will be reset – which will clear this bit field to
“000” and maintain CKE signals de-asserted. After internal reset is de-
asserted, CKE signals remain de-asserted until this field is written to a
value different than “000”. On this event, all CKE signals are asserted.
During entry to other low power states (C3, S1), MCH internal signal
triggers DRAM controller to flush pending commands and enter all ranks
into Self-Refresh mode. During exit to normal mode, MCH signal triggers
DRAM controller to exit Self-Refresh and resume normal operation without
S/W involvement.
001 = NOP Command Enable – All processor cycles to DRAM result in a NOP
command on the DRAM interface.
010 = All Banks Pre-charge Enable – All processor cycles to DRAM result in an
“all banks precharge” command on the DRAM interface.
011 = Mode Register Set Enable – All processor cycles to DRAM result in a
“mode register” set command on the DRAM interface. Host address lines
are mapped to DRAM address lines in order to specify the command sent.
Host address lines [12:3] are mapped to MA[9:0], and HA[13] is mapped
to MA[11].
101 = Reserved
110 = CBR Refresh Enable – In this mode all processor cycles to DRAM result in
a CBR cycle on the DRAM interface
111 = Normal operation
3:2
Reserved
1:0 RO
DRAM Type (DT).
This field is used to select between supported SDRAM types.
This bit is controlled by the MTYPE strap signal.
00 = Reserved
01 = Reserved
10 = Second Revision Dual Data Rate (DDR2) SDRAM
11 = Reserved
Содержание 82925X
Страница 78: ...Host Bridge DRAM Controller Registers D0 F0 R 78 Intel 82925X 82925XE MCH Datasheet...
Страница 98: ...EPBAR Registers Egress Port Register Summary R 98 Intel 82925X 82925XE MCH Datasheet...
Страница 108: ...DMIBAR Registers Direct Media Interface DMI RCRB R 108 Intel 82925X 82925XE MCH Datasheet...
Страница 156: ...Host PCI Express Graphics Bridge Registers D1 F0 R 156 Intel 82925X 82925XE MCH Datasheet...
Страница 172: ...System Address Map R 172 Intel 82925X 82925XE MCH Datasheet...
Страница 192: ...Electrical Characteristics R 192 Intel 82925X 82925XE MCH Datasheet...
Страница 220: ...Ballout and Package Information R 220 Intel 82925X 82925XE MCH Datasheet Figure 12 3 MCH Package Dimensions MCH...