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Theory of Operation

SATA Programmer’s Reference Manual

Figure 5. Compatible Configuration - Option 3b

S-ATA

P-ATA

Port 0

Port 1

Loical Primary

Channel

Intel® ICH5

Physical Primary

Channel

Not Used

Logical Secondary

Channel

Note:

In the figure above, devices represented by dotted lines may be attached, but are not accessible to
software.

•

If SATA is the

secondary

channel and P-ATA is the

primary

channel and Port 0 device is

secondary

master

and Port 1 device is secondary

slave

then

MAP.MV

== ‘110b’. Figure 6

illustrates this configuration:

Figure 6. Compatible Configuration - Option 3c

S-ATA

P-ATA

Port 0

Port 1

Logical Secondary

Channel

Intel® ICH5

Physical Secondary

Channel

Not Used

Logical Primary

Channel

Note:

In the figure above, devices represented by dotted lines may be attached, but are not accessible to
software.

•

If SATA is the

secondary

channel and P-ATA is the

primary

channel and Port 0 device is

secondary

slave

and Port 1 device is secondary

master

then

MAP.MV

== ‘111b’. Figure 7

illustrates this configuration:

Содержание 82801EB

Страница 1: ...Intel 82801EB ICH5 and Intel 82801ER ICH5R Serial ATA Controller Programmer s Reference Manual PRM July 2003 Document Number 252671 002 R...

Страница 2: ...ke changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined...

Страница 3: ...set 09h 21 4 2 2 MAP Register Programming 23 4 3 PCS Port Control and Status Register Offset 92h 23 4 3 1 1 Port Enabling Disabling 24 4 3 1 1 1 BIOS Considerations 24 4 3 1 1 2 Enabling Disabling a S...

Страница 4: ...Option 3a 18 Figure 5 Compatible Configuration Option 3b 19 Figure 6 Compatible Configuration Option 3c 19 Figure 7 Compatible Configuration Option 3d 20 Figure 8 Enhanced Configuration 21 Figure 9 P...

Страница 5: ...5 Revision History Revision Number Description Revision Date 001 Initial Release April 2003 002 Updated register bit names to match Intel 82801EB I O Controller Hub 5 ICH5 Intel 82801ER I O Controlle...

Страница 6: ...R 6 SATA Programmer s Reference Manual This page is intentionally left blank...

Страница 7: ...iable operation of the platform This document will be supplemented from time to time with specification updates The specification updates contain information relating to the latest programming changes...

Страница 8: ...Introduction R 8 SATA Programmer s Reference Manual This page is intentionally left blank...

Страница 9: ...Code SCC bits 0 7 implemented within the Class Code CC offset 0Ah register in the PCI Configuration space Offset 0Ah Class Code Register CC Bits Type Reset Description 15 08 RO 01h Base Class Code BC...

Страница 10: ...Conventions R 10 SATA Programmer s Reference Manual This page is intentionally left blank...

Страница 11: ...ing requirements Has its Programming Interface register set for legacy mode Shall interrupt via IRQ14 primary channel and IRQ15 secondary channel Command and control block are accessed at fixed I O lo...

Страница 12: ...wo serial ATA devices The flexibility and software transparency of the SATA host controller presents an interesting problem for older operating systems that do not comprehend or support the native mod...

Страница 13: ...nd SATA controller can be configured to consume legacy resources see Section 3 1 Legacy Sub Mode that causes the issues i e the primary and secondary channel interfaces will attempt to share the same...

Страница 14: ...ology and may result in undefined behavior Bit Type Reset Description 7 3 RO 0 Reserved 2 0 RW 000 Map Value MV The value in the bits below indicate the address range the SATA port responds to and whe...

Страница 15: ...is configuration system BIOS 1 Shall not program the SATA Device 31 Function 2 controller s base address registers Offsets 10h 24h in PCI configuration space 2 Shall disable access to the SATA control...

Страница 16: ...ding from the slave device registers will return all 1 The Drive Head register offset 06h in the command block is the exception To enable this configuration system BIOS 1 Shall not program the P ATA D...

Страница 17: ...ne P ATA device maximum of two are connected to both SATA and P ATA host controllers and are both accessible by software This configuration is referred to as the combined mode In combined mode of oper...

Страница 18: ...will insure that operating system configuration software does not enumerate and configure the P ATA function 4 Shall program the MAP MV register as follows If SATA is the primary channel and P ATA is...

Страница 19: ...Port 0 device is secondary master and Port 1 device is secondary slave then MAP MV 110b Figure 6 illustrates this configuration Figure 6 Compatible Configuration Option 3c S M S ATA P ATA Port 0 Port...

Страница 20: ...is intended for those operating systems e g Microsoft Windows 2000 Windows XP that comprehend both legacy and native modes of operation It is the preferred configuration for system software due to the...

Страница 21: ...d for either native mode only or a combination of legacy and native modes This is controlled via the Programming Interface register The programming interface register is found in both the SATA and P A...

Страница 22: ...A Device 31 Function 2 P ATA Device 31 Function 1 POP_MODE_SEL SOP_MODE_SEL POP_MODE_SEL SOP_MODE_SEL 1 1 0 0 Note The SATA and P ATA host controllers do not support the programming of the primary and...

Страница 23: ...provide better power management and device presence capabilities the SATA host controller implements a Port Control and Status PCS register The PCS register provides improved power savings in that it...

Страница 24: ...1 for Port 1 bits to be accurate See Section 4 4 1 Hardware and Software Considerations As part of a robust power conservation strategy a port on the ICH5 SATA host controller should be disabled when...

Страница 25: ...e control methods can be used to supplement the device power management and are executed whenever the operating system wishes to place the SATA into the D0 and D3 power states respectively control met...

Страница 26: ...and Software Considerations The value of the port presence bits is valid only under the following conditions The SATA host controller is in the D0 power state The port to be checked is enabled Note Th...

Страница 27: ...ent v1 0 specification this document is available from the Serial ATA Working Group at http www serialata org This duration is highly dependent on the manufacturer of the SATA device The time value z...

Страница 28: ...h the logical primary and secondary channels WDM device drivers can only execute control methods associated with their corresponding _ADR object in ACPI namespace of which there is a direct relationsh...

Страница 29: ...ting the Intel ICH5 SATA Host Controller in ACPI Namespace See Appendix B Example ACPI Namespace for an example of an ACPI namespace for the ICH5 SATA host controller This example supports the ICH5 SA...

Страница 30: ...Theory of Operation R 30 SATA Programmer s Reference Manual This page is intentionally left blank...

Страница 31: ...how a WDM driver could read write the PCS PxE bits for enabling or disabling the SATA port s This example assumes direct access to the SATA PCI Configuration space Disable the ports For simplicity we...

Страница 32: ...config space to read write Length size of pBuf Exit returns NT_SUCCESS if no errors NTSTATUS ReadWriteConfigSpace PDEVICE_OBJECT pDO BOOLEAN fRead PVOID pBuf ULONG Offset ULONG Length KEVENT event PIR...

Страница 33: ...is sample ASL code demonstrates how to enable and disable the SATA port s from the _PS0 and _PS3 control methods OperationRegion IDEC PCI_Config 0x90 3 Field IDEC ByteAcc NoLock Preserve MAP 8 SATA Ma...

Страница 34: ...ing Port 0 If LAnd Arg0 0x01 If LAnd Local2 0x10 Decrement Local1 Port 0 is enabled Else Since a device detect failed we disable the port This will insure that the port remains disabled this is not re...

Страница 35: ...settings In Combined mode both SATA ports are viewed as a single logical channel implementing a master slave configuration in which case both ports are enabled Enable Power to the device Set the GPIO...

Страница 36: ...l Name _ADR 1 Logical secondary channel Port 0 or 1 BIOS selectable Device DRV0 Logical secondary master Name _ADR 0 Handle transitions to D0 power state Method _PS0 0 make sure the OS drivers finds t...

Страница 37: ...ed here dependent on the MAP settings In Combined mode both SATA ports are viewed as a single logical channel implementing a master slave configuration in which case both ports are disabled Store Zero...

Страница 38: ...primary channel if bMAP 0x06 Not P ATA device Must be SATA if bPCS 0x10 iPort0Status 1 Port 0 device present if bPCS 0x20 iPort1Status 1 Port 1 device present Now we need to figure out which is master...

Страница 39: ...DM device drivers can only execute control methods associated with their corresponding _ADR object in ACPI namespace of which there is a direct relationship between the _ADR object and the PDO This sa...

Страница 40: ...device present 1 Device presence unknown NTSTATUS SATA_CheckPortStatus IN PDEVICE_OBJECT pDO PDWORD pdwStatus NTSTATUS status STATUS_SUCCESS PACPI_METHOD_ARGUMENTpArgBuf ACPI_EVAL_INPUT_BUFFER InputBu...

Страница 41: ...Irp to ACPI Entry Pdo target of the request Ioctl the request InputBuffer ptr to input parameters InputSize size of InputBuffer OutputBuffer ptr to receive results OutputSize size of OutputBuffer Exi...

Страница 42: ...k MajorFunction IRP_MJ_DEVICE_CONTROL Pass the request to the Pdo always wait for the completion routine status IoCallDriver Pdo Irp if status STATUS_PENDING Wait for the IRP to be completed then grab...

Страница 43: ...umes BIOS populated the SATA timing registers appropriately depending on which port is configured as primary and secondary This control method determines if device s are present on the logical primary...

Страница 44: ...x20 Store One Local4 Port 1 device present Now we need to figure out which is master and slave if applicable If LNot LAnd Local1 0x01 is Port 0 master Port 0 is master Store Local3 Local5 If LAnd Loca...

Страница 45: ...rn 0xffffffff Device DRV0 Logical primary master Name _ADR 0 Device SECD Secondary channel Method GSPS 0 Get the port status Similar to GSPS for PRID Name _ADR 1 Logical secondary channel Port 0 or 1...

Страница 46: ...Theory of Operation R 46 SATA Programmer s Reference Manual This page is intentionally left blank...

Страница 47: ...y master Port 1 logical primary master Note that a separate P ATA device namespace is required in the event that non Combined mode is used If in Combined mode P ATA and SATA combined as a single PCI f...

Страница 48: ...non combined modes Entry arg0 bit map indicating which port s to enable bit 0 set enable Port 0 bit 1 set enable Port 1 all other bits must be zero Since the ports operate independently we can enable...

Страница 49: ...This method determines the type of device being managed by the specified logical channel Entry Arg0 specifies which channel is to be checked 0 Primary 1 Secondary Exit Returns 0 if the channel is host...

Страница 50: ...P 0x1 LLess MAP 0x6 Store 0x1 Local0 SATA is primary combined Else If LEqual MAP Zero Store 3 Local0 port 0 is primary master If LEqual MAP One Store 4 Local0 port 1 is primary master Else Check the s...

Страница 51: ...logical primary master or P ATA Primary master slave Device PRID Name _ADR 0 Logical primary channel Port 0 1 BIOS selectable or P_ATA Method _GTM similar to current P ATA implementations Method _STM...

Страница 52: ...30 power must be applied for at least 30ms Store 0x03 Local1 is combined enable both ports If LEqual Local0 3 Enable Power to the device platform specific Sleep 30 power must be applied for at least...

Страница 53: ...gical channel implementing a master slave configuration in which case both ports are disabled If LEqual Local0 1 Store 0x0 PCS is combined disable both ports If LEqual Local0 3 NAnd PCS 0x01 PCS only...

Страница 54: ...n configured for Combined mode In non Combined mode SATA devices use a master master arrangement Device DRV1 Logical primary slave SATA Port 0 1 or P ATA device 1 Name _ADR 1 similar to current P ATA...

Страница 55: ...ary master or P ATA logical secondary master slave Device SECD Name _ADR 1 Method _GTM similar to current P ATA implementations Method _STM 3 similar to current P ATA implementations Like the _GTF met...

Страница 56: ...x03 Local1 is combined enable both ports If LEqual Local0 5 Enable Power to the device platform specific Sleep 30 power must be applied for at least 30ms Store 0x01 Local1 only enable port 0 If LEqual...

Страница 57: ...rts are disabled If LEqual Local0 2 Store 0x0 PCS is combined disable both ports If LEqual Local0 5 NAnd PCS 0x01 PCS only disable port 0 If LEqual Local0 6 NAnd PCS 0x02 PCS only disable port 1 Disab...

Страница 58: ...Combined mode SATA devices use a master master arrangement Device DRV1 Logical secondary slave SATA Port 0 1 or P ATA device 1 Name _ADR 1 similar to current P ATA implementations Since this device no...

Страница 59: ...Theory of Operation R SATA Programmer s Reference Manual 59...

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