82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide
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Crucial tests are as follows, listed in priority order:
1. Bit Error Rate (BER). This test is a good indicator of real world network performance. It
should be done with long and short cables and many link partners. The test limit is 10 to 11
errors (10/100/1000 Mbps).
2. Output Amplitude, Rise and Fall Time (10/100 Mbps), Symmetry and Droop (1000 Mbps).
For the 82541xx controller, use the appropriate PHY test waveform.
3. Return Loss. This test indicates proper impedance matching, measured through the RJ-45
connector back toward the magnetics module.
4. Jitter Test (10/100 Mbps) or Unfiltered Jitter Test (1000 Mbps). This test indicates clock
recovery ability (master and slave for Gigabit controller).
5. Harmonic Content for 10 Mbps.
6. Output Symmetry for 100/1000 Mbps.
7. Rise and Fall Time for 100 Mbps.
8. Droop for 1000 Mbps.
9. Duty Cycle Distortion for 100 Mbps.
4.5
Troubleshooting Common Physical Layout Issues
The following is a list of common physical layer design and layout mistakes in LAN on
Motherboard designs.
1. Unequal length of the two traces within a differential pair. Inequalities create common-mode
noise and will distort the transmit or receive waveforms.
2. Lack of symmetry between the two traces within a differential pair. Asymmetry can create
common-mode noise and distort the waveforms. For each component or via that one trace
encounters, the other trace should encounter the same component or a via at the same distance
from the Ethernet silicon.
3. Excessive distance between the Ethernet silicon and the magnetics. Long traces on FR4
fiberglass epoxy substrate will attenuate and distort the analog signals. In addition, any
impedance mismatch in the traces will be aggravated if they are longer than the four inch rule.
4. Routing any other trace parallel to and close to one of the differential traces. Crosstalk getting
onto the receive channel will cause degraded long cable BER. Crosstalk getting onto the
transmit channel can cause excessive EMI emissions and can cause poor transmit BER on long
cables. At a minimum, other signals should be kept 0.1 inch from the differential traces.
5. Routing one pair of differential traces too close to another pair of differential traces. After
exiting the Ethernet silicon, the trace pairs should be kept 0.1 inch or more away from the
other trace pairs. The only possible exceptions are in the vicinities where the traces enter or
exit the magnetics, the RJ-45 connector, and the Ethernet silicon.
6. Using a low quality magnetics module.
7. Re-use of an out-of-date physical layer schematic in an Ethernet silicon design. The
terminations and decoupling can be different from one PHY to another.
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