Intel
®
81341 and 81342—Peripheral Bus Interface Unit
Intel
®
81341 and 81342 I/O Processors
Developer’s Manual
December 2007
720
Order Number: 315037-002US
9.3.3
Determining Block Sizes for Memory Windows
The memory window size can be determined by writing ones to the appropriate upper
bits of the limit register. The binary-weighted value of the first non-zero bit set in the
limit register indicates the size of the memory window.
describes the
relationship between limit register values and the byte sizes of the memory window.
As an example, assume that FFF0 0000H is written to the PBI Limit Register 0 (PBLR0).
Scanning upwards starting at bit 12, bit 20 is the first one bit found. The binary-
weighted value of this bit is 1,048,576, indicating a 1 Mbyte of memory window.
When programming the Base and Limit Registers for a memory window, the Base
Address always needs to be aligned the size of the memory window set in a limit
register. For a 1 Mbyte memory window, only bit 20 through bit 31 of the base address
from the PBI Base Address Register 0 (PBBAR0) are relevant to the PBI when decoding
Memory Window 0.
Warning:
A given PBI Base (PBBAR0-PBBAR1) and Limit (PBLR0-PBLR1) register pair should not
be modified during the time there is activity on the peripheral bus associated with that
particular peripheral memory window. For instance, following boot-up, code executing
from Peripheral Memory Window 0 may be used to modify the PBI Base and Limit
registers for Peripheral Memory Window 1, but
not
for Peripheral Memory Window 0.
Table 436. Memory Block Size Limit Register Values
Limit Register Value
a
a. Smallest Limit Register Value is 4 KBytes.
Size
(in Bytes)
Limit Register Value
Size
(in Bytes)
FFFFF000H
4K
FF800000H
8 M
FFFFE000H
8K
FF000000H
16 M
FFFFC000H
16K
FE000000H
32 M
FFFF8000H
32K
FC000000H
Address
Window
Closed.
FFFF0000H
64K
F8000000H
FFFE0000H
128K
F0000000H
FFFC0000H
256K
E0000000H
FFF80000H
512K
C0000000H
FFF00000H
1 M
80000000H
FFE00000H
2 M
00000000H
FFC00000H
4 M