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*

Other brands and names are the property of their respective owners.

Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or

copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Intel retains the right to make

changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

June 2004

         

COPYRIGHT ©INTEL CORPORATION, 2004

Order   Number:  270501-008

80C51FA/83C51FA

EVENT-CONTROL CHMOS SINGLE-CHIP

8-BIT MICROCONTROLLER

Automotive

Y

Extended Automotive
Temperature Range
(

b

40

§

C to

a

125

§

C Ambient)

Y

High Performance CHMOS Process

Y

Three 16-Bit Timer/Counters
 - Timer 2 is an Up/Down

Timer/Counter

Y

Programmable Counter Array with:
- High Speed Output
- Compare/Capture
- Pulse Width Modulator
- Watchdog Timer Capabilities

Y

8K On-Chip ROM

Y

256 Bytes of On-Chip Data RAM

Y

Boolean Processor

Y

32 Programmable I/O Lines

Y

7 Interrupt Sources

Y

Programmable Serial Channel with:
- Framing Error Detection
- Automatic Address Recognition

Y

TTL and CMOS Compatible Logic
Levels

Y

64K External Program Memory Space

Y

64K External Data Memory Space

Y

MCS

É

51 Microcontroller

Fully

Compatible Instruction

Set

Y

Power Saving Idle and Power Down
Modes

Y

ONCE (On-Circuit Emulation) Mode

Y

Available in PLCC and PDIP Packages

(See Packaging Specification, Order

Ý

231369)

Y

Available in 12 MHz and 16 MHz
Versions

MEMORY ORGANIZATION

PROGRAM MEMORY: Up to 8 Kbytes of the program memory can reside in the on-chip ROM. In addition the
device can address up to 64K of program memory external to the chip.

DATA MEMORY: This microcontroller has a 256 x 8 on-chip RAM. In addition it can address up to 64 Kbytes of

external data memory.

The Intel 80C51FA/83C51FA is a single-chip control oriented microcontroller which is fabricated on Intel's

CHMOS III (83C51FA) ROM technology. For the remainder of this datasheet references to the ROMless

(80C51FA) and ROM (83C51FA) versions will be denoted as 83C51FA. Being a member of the MCS

É

51

microcontroller family, the 83C51FA uses the same powerful instruction set, has the same architecture, and is

pin-for-pin compatible with the existing MCS 51 microcontroller products. The 83C51FA is an enhanced

version of the 87C51. It's added features make it an even more powerful microcontroller for applications that

require Pulse Width Modulation, High Speed I/O, and up/down counting capabilities such as brake and

traction control. It also has a more versatile serial channel that facilitates multi-processor communications.

NOTICE:

This datasheet contains information on products in full production. Specifications within this datasheet

are subject to change without notice. Verify with your local Intel sales office that you have the latest

datasheet before finalizing a design.

Содержание 80C51FA

Страница 1: ...Power Down Modes Y ONCE On Circuit Emulation Mode Y Available in PLCC and PDIP Packages See Packaging Specification Order 231369 Y Available in 12 MHz and 16 MHz Versions MEMORY ORGANIZATION PROGRAM M...

Страница 2: ...AUTOMOTIVE 80C51FA 83C51FA 270501 1 Figure 1 83C51FA Block Diagram 2...

Страница 3: ...are guaranteed over the temperature range of 40 C to 85 C ambient For the automo tive temperature range option operational charac teristics are guaranteed over the temperature range of 40 C to 125 C...

Страница 4: ...l features of the 83C51FA Port Pin Alternate Function P1 0 T2 External Count Input to Timer Counter 2 P1 1 T2EX Timer Counter 2 Capture Reload Trigger and Direction Control P1 2 ECI External Count Inp...

Страница 5: ...ead strobe to external Program Memory When the 83C51FA is executing code from external Program Memory PSEN is activated twice each ma chine cycle except that two PSEN activations are skipped during ea...

Страница 6: ...is serviced the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down DESIGN CONSIDERATION When the Idle mode is terminated by a har...

Страница 7: ...is not recommended and ex tended exposure beyond the Operating Conditions may affect device reliability DC CHARACTERISTICS TA e b40 C to a125 C VCC e 5V g10 VSS e 0V Symbol Parameter Min Typ Max Unit...

Страница 8: ...pFs the noise pulse on the ALE signal may exceed 0 8V In these cases it may be desirable to qualify ALE with a Schmitt Trigger or use an Address Latch with a Schmitt Trigger Strobe input 2 Capacitive...

Страница 9: ...s Frequency 270501 8 TCLCH e TCHCL e 5 ns Figure 7 ICC Test Condition Active Mode All other pins disconnected 270501 9 TCLCH e TCHCL e 5 ns Figure 8 ICC Test Condition Idle Mode All other pins disconn...

Страница 10: ...h 127 2TCLCLb40 ns TAVLL Address Valid to ALE Low 43 TCLCLb40 ns TLLAX Address Hold After ALE Low 53 TCLCLb30 ns TLLIV ALE Low to Valid Instruction In 224 4TCLCLb110 ns TLLPL ALE Low to PSEN Low 53 TC...

Страница 11: ...AUTOMOTIVE 80C51FA 83C51FA EXTERNAL PROGRAM MEMORY READ CYCLE 270501 12 EXTERNAL DATA MEMORY READ CYCLE 270501 13 EXTERNAL DATA MEMORY WRITE CYCLE 270501 14 11...

Страница 12: ...etup to Clock 700 10TCLCLb133 ns Rising Edge TXHQX Output Data Hold after 50 2TCLCLb117 ns Clock Rising Edge TXHDX Input Data Hold After Clock 0 0 ns Rising Edge TXHDV Clock Rising Edge to Input 700 1...

Страница 13: ...RST pin is now RESET pin 3 RST pin description is now RESET pin description 4 Figure 6 ICC vs Frequency has been corrected to show test conditions 5 ICC Max spec has been corrected 6 A C Characterist...

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