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80960MC

Figure 27. Interrupt Acknowledge Transaction

CLK2

INTR

LAD31:0

ALE

ADS

INTA

DT/R

DEN

LOCK

READY

NOTE:
INTR can go low no sooner than the input hold time following the beginning of interrupt acknowledgment cycle 1.
For a second interrupt to be acknowledged, INTR must be low for at least three cycles before it can be reasserted.

INTERRUPT

ACKNOWLEDGEMENT

CYCLE 1

IDLE

(5 BUS STATES)

INTERRUPT

ACKNOWLEDGEMENT

CYCLE 2

CYCLE

ADDR

VECTOR

ADDR

CLK

Содержание 80960MC

Страница 1: ... Local 32 Bit Registers Four Local Register Sets Stored On Chip Sixteen 32 Bit Registers per Set Register Scoreboarding On Chip Memory Management Unit 4 Gbyte Virtual Address Space per Task 4 Kbyte Pages with Supervisor User Protection Built in Interrupt Controller 32 Priority Levels 248 Vectors Supports M8259A 3 4 µs Latency 25 MHz Easy to Use High Bandwidth 32 Bit Bus 66 7 Mbytes s Burst Up to 1...

Страница 2: ...ended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Intel retains the right to make changes to specifications and product descriptions at any time without not...

Страница 3: ... 7 1 1 13 Interrupt Handling 8 1 1 14 Debug Features 8 1 1 15 Fault Detection 8 1 1 16 Inter Agent Communications IAC 9 1 1 17 Built in Testability 9 1 1 18 Compatibility with 80960K Series 9 1 1 19 CHMOS 9 2 0 ELECTRICAL SPECIFICATIONS 13 2 1 Power and Grounding 13 2 2 Power Decoupling Recommendations 13 2 3 Connection Recommendations 13 2 4 Characteristic Curves 13 2 5 Test Load Circuit 16 2 7 D...

Страница 4: ...re 19 132 Lead Pin Grid Array PGA Package 23 Figure 20 80960MC PGA Pinout View from Bottom Pins Facing Up 24 Figure 21 80960MC PGA Pinout View from Top Pins Facing Down 25 Figure 22 25 MHz Maximum Allowable Ambient Temperature 29 Figure 23 Non Burst Read and Write Transactions Without Wait States 30 Figure 24 Burst Read and Write Transaction Without Wait States 31 Figure 25 Burst Write Transaction...

Страница 5: ...rs must be easy to use in both hardware and software designs All members of the i960 processor family share a common core architecture which utilizes RISC tech nology so that except for special functions the family members are object code compatible Each new processor in the family adds its own special set of functions to the core to satisfy the needs of a specific application or range of applicat...

Страница 6: ...ate the instruction alignment stage in the pipeline To simplify the instruction decoder there are only five instruc tion formats each instruction uses only one format See Figure 3 5 Overlapped Instruction Execution Load operations allow execution of subsequent instructions to continue before the data has been returned from memory so that these instructions can overlap the load The 80960MC manages ...

Страница 7: ...ot Nand Rotate Comparison Branch Bit and Bit Field String Compare Conditional Compare Compare and Increment Compare and Decrement Unconditional Branch Conditional Branch Compare and Branch Set Bit Clear Bit Not Bit Check Bit Alter Bit Scan For Bit Scan Over Bit Extract Modify Move String Move Quick String Fill String Compare String Scan Byte for Equal Conversion Decimal Call Return Arithmetic Conv...

Страница 8: ... and Fortran Table 2 lists the memory accessing modes 1 1 2 Data Types The 80960MC recognizes the following data types Numeric 8 16 32 and 64 bit ordinals 8 16 32 and 64 bit integers 32 64 and 80 bit real numbers Non Numeric Bit Bit Field Triple Word 96 bits Quad Word 128 bits 1 1 3 Large Register Set The 80960MC programming environment includes a large number of registers 36 registers are availab...

Страница 9: ...am but consist of many branches loops and procedure calls that lead to jumping back and forth in the same small section of code Thus by maintaining a block of instructions in cache the number of memory references required to read instructions into the processor is greatly reduced To load the instruction cache instructions are fetched in 16 byte blocks up to four instructions can be fetched at one ...

Страница 10: ...upervisor 00 No Access Read Only 01 No Access Read Write 10 Read Only Read Write 11 Read Write Read Write 1 1 8 Floating Point Arithmetic In the 80960MC floating point arithmetic is an integral part of the architecture Having the floating point unit integrated on chip provides two advan tages First it improves the performance of the chip for floating point applications since no additional bus over...

Страница 11: ...s of ports can be carried out independently of the operating system Once the ports have been set up by the programmer the processor handles the message passing automatically 1 1 11 High Bandwidth Local Bus The 80960MC CPU resides on a high bandwidth address data bus known as the local bus L Bus The L Bus provides a direct communication path between the processor and the memory and I O subsystem in...

Страница 12: ...d the Trace Controls Word By setting bits in these control words a software debug monitor can closely control how the processor responds during program execution The 80960MC has both hardware and software breakpoints It provides two hardware breakpoint registers on chip which by using a special command can be set to any value When the instruction pointer matches either breakpoint register value th...

Страница 13: ...sh between problems caused by processor failure and problems resulting from other causes 1 1 18 Compatibility with 80960K Series Application programs written for the 80960K Series microprocessors can be run on the 80960MC without modification The 80960K Series instruction set forms the core of the 80960MC s instructions so binary compatibility is assured 1 1 19 CHMOS The 80960MC is fabricated usin...

Страница 14: ...s not asserted When the pin is not asserted the processor asserts LOCK during the Ta cycle of the read trans action The processor deasserts LOCK in the Ta cycle of the write transaction During the time LOCK is asserted a bus agent can perform a normal read or write but not a RMW operation The processor also asserts LOCK during interrupt acknowledge transactions Do not leave LOCK unconnected It mus...

Страница 15: ... input output signal that during Td and Tw cycles identifies the contents of a 32 bit word as either data TAG 0 or an access descriptor TAG 1 Table 5 80960MC Pin Description Support Signals Sheet 1 of 2 NAME TYPE DESCRIPTION BADAC I BAD ACCESS when asserted in the cycle following the one in which the last READY of a transaction is asserted indicates that an unrecoverable error has occurred on the ...

Страница 16: ...SOR NUMBER this signal is interpreted differently during system reset When the signal is a high voltage level it indicates that this processor is a primary bus master local processor number 0 When at a low voltage level it indicates that this processor is a secondary bus master local processor number 1 INT1 I INTERRUPT 1 like INT0 provides direct interrupt signaling INT2 INTR I INTERRUPT2 INTERRUP...

Страница 17: ...uld ever be left floating All open drain outputs require a pull up device While in most cases a simple pull up resistor is adequate a network of pull up and pull down resis tors biased to a valid VIH 3 0 V and terminated in the characteristic impedance of the circuit board is recommended to limit noise and AC power consumption Figure 5 and Figure 6 show recom mended values for the resistor network...

Страница 18: ...uency Room Temp 60 40 20 0 20 40 60 80 100 120 140 VCC 5 0 V POWER SUPPLY CURRENT mA CASE TEMPERATURE C 25 MHz 20 MHz 16 MHz 380 360 340 320 300 280 260 240 220 200 OPERATING FREQUENCY MHz 4 5V 5 0V 5 5V TYPICAL SUPPLY CURRENT mA TEMP 22 C 400 380 360 340 320 300 280 260 240 220 200 180 16 20 25 ...

Страница 19: ... 260 240 220 200 180 16 20 25 160 Figure 9 Worst Case Voltage vs Output Current on Open Drain Pins Figure 10 Capacitive Derating Curve 0 10 20 30 40 50 0 8 0 6 0 4 0 2 0 0 OUTPUT LOW CURRENT mA TEMP 85 C VCC 4 5V OUTPUT LOW VOLTAGE V 0 20 40 60 80 100 30 25 20 15 10 CAPACITIVE LOAD pF TEMP 85 C VCC 4 5V 5 0 RISING FALLING VALID DELAY ns THREE STATE OUTPUT ...

Страница 20: ...e 80960MC driver under test is turned off the output pin is pulled up to VREF i e VOH Diode D1 is turned off and the IOL current source flows through diode D2 When the 80960MC open drain driver under test is on diode D1 is also on and the voltage on the pin being tested drops to VOL Diode D2 turns off and IOL flows through diode D1 Figure 11 Test Load Circuit for Three State Output Pins Figure 12 ...

Страница 21: ... 0 VCC 0 3 V VCL CLK2 Input Low Voltage 0 3 0 8 V VCH CLK2 Input High Voltage 0 55 VCC VCC 0 3 V VOL Output Low Voltage 0 45 V 1 2 VOH Output High Voltage 2 4 V 3 4 ICC Power Supply Current 16 MHz 20 MHz 25 MHz 315 360 420 mA mA mA 5 5 5 ILI Input Leakage Current 15 µA 0 VIN VCC ILO Output Leakage Current 15 µA 0 45 VO VCC CIN Input Capacitance 10 pF fC 1 MHz 6 CO Output Capacitance 12 pF fC 1 MHz...

Страница 22: ...he TTL levels of LOW 0 8 V or HIGH 2 0 V All AC testing should be done with input voltages of 0 4 V and 2 4 V except for the clock CLK2 which should be tested with input voltages of 0 45 V and 0 55 VCC Figure 13 Drive Levels and Timing Relationships for 80960MC Signals A B C D A B C 1 5V 1 5V 1 5V 1 5V 0 8V T6 1 5V 1 5V T7 1 5V 1 5V VALID OUTPUT T6 T8 T8 T13 T14 1 5V 1 5V VALID OUTPUT T9 2 0V 2 0V...

Страница 23: ...Relationship A4484 01 READY DEN DT R W R BE 0 3 ADS ALE LAD 31 0 CLK CLK2 T11 T12 T11 T12 T11 T12 T6 T6 T6 T6 T9 T13 T 14 T9 T13 14 T T7 T6 Address Data T13 T8 T14 T9 T10 T11 T6 T13 Address Data T9 T6 T9 T8 T7 T T T a d r T T T a d r T2 T3 Td T1 T9 CLK CLK2 T Ta Td r Bus State Bus State Bus State ...

Страница 24: ...e CLK2 5 ns VIL 10 Point 1 2V T3 Processor Clock High Time CLK2 5 ns VIH 90 Point 0 1V 0 5 VCC T4 Processor Clock Fall Time CLK2 10 ns VIN 90 Point to 10 Point 1 T5 Processor Clock Rise Time CLK2 10 ns VIN 10 Point to 90 Point 1 Synchronous Outputs T6 Output Valid Delay 2 18 ns T6H HLDA Output Valid Delay 4 23 ns T7 ALE Width 12 ns T8 ALE Output Valid Delay 2 18 ns T9 Output Float Delay 2 18 ns 2 ...

Страница 25: ...EL MIN 0 55VCC LOW LEVEL MAX 0 8V T1 T3 T5 T4 T2 90 10 1 5 V CLK2 CLK RESET OUTPUTS FIRST A B C D A INIT PARAMETERS BADAC INT0 IAC MUST BE SET UP 8 CLOCKS PRIOR TO THIS CLK2 EDGE INIT PARAMETERS MUST BE HELD BEYOND THIS CLK2 EDGE T15 RESET HOLD T16 RESET SETUP T17 RESET WIDTH T15 T16 T17 ...

Страница 26: ...ocessor must have sampled any inputs for the previous state Similarly whenever the processor generates an output that indicates a transition into a subsequent state any outputs that are specified to be three stated in this new state are guaranteed to be three stated 3 0 MECHANICAL DATA 3 1 Packaging The 80960MC is available in one package type a 132 lead ceramic pin grid array PGA Pins are arrange...

Страница 27: ...80960MC 23 Figure 19 132 Lead Pin Grid Array PGA Package 1 2 3 A B C D E F G H J K L M N P 4 5 6 7 8 9 10 11 12 13 14 ...

Страница 28: ...EADY LAD30 CACHE LAD31 LAD29 LAD27 LAD26 LAD28 HLDA ADS ALE N C N C N C N C N C N C N C N C N C N C N C N C N C N C N C N C N C N C N C N C VSS VCC VSS VCC VSS VSS VSS VSS VCC VCC VCC VCC INT2 INT0 INT1 INT3 LAD3 LAD8 LAD20 LAD13 BADAC HOLD LAD25 RESET LAD0 LAD1 LAD4 LAD5 LAD7 LAD9 LAD11 LAD14 LAD16 LAD17 LAD19 LAD2 LAD6 LAD10 LAD12 LAD15 LAD18 LAD21 LAD22 LAD24 LAD23 CLK2 P N M L K J H G F E D C ...

Страница 29: ...AD31 LAD29 LAD27 LAD26 LAD28 HLDA ADS ALE N C N C N C N C N C N C N C N C N C N C N C N C N C N C N C N C N C N C N C N C VSS VCC VSS VCC VSS VSS VSS VSS VCC VCC VCC VCC INT2 INT0 INT1 INT3 LAD3 LAD8 LAD20 LAD13 BADAC HOLD LAD25 RESET LAD0 LAD1 LAD4 LAD5 LAD7 LAD9 LAD11 LAD14 LAD16 LAD17 LAD19 LAD2 LAD6 LAD10 LAD12 LAD15 LAD18 LAD21 LAD22 LAD24 LAD23 CLK2 P N M L K J H G F E D C B A P N M L K J H ...

Страница 30: ... C A12 LAD1 D3 HLDA HOLDR J14 N C N7 N C A13 INT2 INTR D12 VCC K1 BE3 N8 N C A14 VCC D13 N C K2 FAILURE N9 N C B1 LAD23 D14 N C K3 VSS N10 N C B2 LAD24 E1 LAD28 K12 VCC N11 N C B3 LAD22 E2 LAD26 K13 N C N12 N C B4 LAD21 E3 LAD27 K14 N C N13 N C B5 LAD18 E12 N C L1 DEN N14 N C B6 LAD15 E13 VSS L2 N C P1 VCC B7 LAD12 E14 N C L3 VCC P2 N C B8 LAD10 F1 LAD29 L12 VSS P3 N C B9 LAD6 F2 LAD31 L13 N C P4 ...

Страница 31: ... K2 LAD26 E2 N C M13 VCC D12 HLDA HOLDR D3 LAD27 E3 N C M14 VCC K12 HOLD HLDAR C1 LAD28 E1 N C N2 VCC L3 IAC INT0 C14 LAD29 F1 N C N3 VCC M2 INT1 C13 LAD30 G1 N C N4 VCC M5 INT2 INTR A13 LAD31 F2 N C N5 VCC M11 INT3 INTA C12 LOCK H3 N C N6 VCC P1 LAD0 B12 N C D13 N C N7 VCC P14 LAD1 A12 N C D14 N C N8 VSS A2 LAD2 B10 N C E12 N C N9 VSS B14 LAD3 C9 N C E14 N C N10 VSS C5 LAD4 A11 N C F12 N C N11 VS...

Страница 32: ...re 23 Figure 24 and Figure 25 The curves assume the maximum permitted supply current ICC at each speed VCC of 5 0 V and a TCASE of 85 C PGA Table 10 80960MC PGA Package Thermal Characteristics Thermal Resistance C Watt Parameter Airflow ft min m sec 0 0 50 0 25 100 0 50 200 1 01 400 2 03 600 3 04 800 4 06 θ Junction to Case 2 2 2 2 2 2 2 θ Case to Ambient No Heatsink 19 18 17 15 12 10 9 θ Case to ...

Страница 33: ...MHz Maximum Allowable Ambient Temperature AIRFLOW ft min TEMPERATURE o C 80 75 70 65 60 55 50 45 40 0 100 200 300 400 500 600 700 800 PGA with no heatsink PGA with omni directional heatsink PGA with uni directional heatsink 85 ...

Страница 34: ...re 25 Burst Write Transaction with 2 1 1 1 Wait States pg 32 Figure 26 Accesses Generated by Quad Word Read Bus Request Misaligned Two Bytes from Quad Word Boundary 1 0 0 0 Wait States pg 33 Figure 27 Interrupt Acknowledge Transaction pg 34 Figure 28 Bus Exchange Transaction PBM Primary Bus Master SBM Secondary Bus Master pg 35 Figure 23 Non Burst Read and Write Transactions Without Wait States Ta...

Страница 35: ...80960MC 31 Figure 24 Burst Read and Write Transaction Without Wait States Ta Td Td Tr Ta Td Td Td Td Tr CLK2 CLK LAD31 0 ALE ADS BE3 0 W R DT R DEN READY ...

Страница 36: ...80960MC 32 Figure 25 Burst Write Transaction with 2 1 1 1 Wait States Ta Tw Tw Td Tw Td Tw Td Tw Td Tr CLK2 CLK LAD31 0 ALE ADS BE3 0 W R DT R DEN READY ...

Страница 37: ...Figure 26 Accesses Generated by Quad Word Read Bus Request Misaligned Two Bytes from Quad Word Boundary 1 0 0 0 Wait States Ta Tw Td Td Td Td Tr Ta Tw Td Tr CLK2 CLK LAD31 0 ALE ADS BE3 2 W R DT R DEN READY BE1 0 ...

Страница 38: ...NOTE INTR can go low no sooner than the input hold time following the beginning of interrupt acknowledgment cycle 1 For a second interrupt to be acknowledged INTR must be low for at least three cycles before it can be reasserted INTERRUPT ACKNOWLEDGEMENT CYCLE 1 IDLE 5 BUS STATES INTERRUPT ACKNOWLEDGEMENT CYCLE 2 PREVIOUS CYCLE ADDR VECTOR ADDR CLK ...

Страница 39: ...Data Data Data Data Addr Th Th Th Th Th Th Th Td Th Thr Thr Thr Ta Td Tr Thr Thr Thr Thr Ta Td Td Ti Ti Th Th Th Th W R LAD0 _ PBM ALE SBM ALE READY SBM HOLDR PBM HOLD PBM HLDA SBM HLDAR PBM BUS STATE SBM BUS STATE To address the fact that many of the package prefix variables have changed all package prefix variables in this document are now indicated with an x 5 0 REVISION HISTORY ...

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