Intel 80331, Руководство по конструкции

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Intel® 80331 I/O Processor Design Guide
Memory Controller
7.4.2 Clock Signal Groups
The 80331 drives the command clock signals required by the DDR interface. The source-clocked
signals are “clocked” into the DIMM using the command clock signals. The 80331 drives the
command clock signals and the source-clocked signals together, these signals can be source
clocked. The 80331 drives the command clock in the center of the valid window, and the
source-clocked signals propagate with the command clock signal. An important timing
specification is the difference between the command clock flight time and the source clocked
signal flight time. The absolute flight time is not as critical.
The common clock signal group contains M_CK[2:0] and M_CK[2:0]# . The following tables and
figure show the routing requirements for the clock signal group.
Table 39. DIMM Clocked Signal Group Termination
DDR SDRAM Rs Series Rp Parallel
22.1 +/- 5% ohms (non-buffered DDR only) none