110
Memory Controller
7.5.4
Embedded Configuration
The following tables provide layout guidelines for applications in which the DDRII 400 memory
SDRAM, registers and PLL components are placed directly on the board without a DIMM.
7.5.4.1
DDRII 400 Embedded Source Synchronous Routine Guidelines
This section lists the recommendations for the DDR II 400 embedded source synchronous routing.
These signals include all the DQ/DQS signals. Refer to
and
for a block diagram
of the lengths and matching requirements.
Table 65.
DDRII 400 Embedded Source Synchronous Routing Recommendations
Parameter
Routing Guideline
Reference Plane
Route over unbroken power plane
Preferred Topology
Stripline
Breakout
5 mils x 5 mils spacing.
Group Trace Spacing (edge to edge)
•
5 mils is acceptable for pin escapes and terminations.
•
5 mils for DQS differential pairs (intra-pair)
•
>12 mils between any DQ/DQS signals
•
>20 mils bust be maintained from any other groups
Trace Impedance
•
45 ohms +/- 15%
•
50 ohms +/- 15%
•
Differential impedance of 100 ohms +/- 15%
Trace Details
•
TL1 and TL4 are approximately same length and the series Termination
to be placed in the middle of lead-in trace for Lead-in lengths >6 Inches
•
When Controller to SDRAM lead-in trace length is less than 6 Inches,
Series Termination may be placed anywhere between middle of the
lead-in trace to SDRAM
•
For DQS use differential routing
•
Route all data signals and associated strobes on same layer as strip lines.
•
No parallel DQS termination is required with ODT of SDRAMs used.
•
Refer to
DQ Group Spacing
Spacing from other DQ groups 20 mils minimum
Trace Lengths
Refer to
for details.
DQS Length Matching:
•
Trace Length Matching within DQS group
•
Within one DQS pair plus and minus
•
Between other DQS groups
•
With respect to the clock signal
+/- 0.05” within DQS group
+/- 0.0250”
+/- 0.250” between each of the DQS groups.
+/- 1” (target motherboard clock to PLL input = +/- 1” of any DQS/DQ pair)
Series Termination
22.1 ohms +/- 5%
Parallel Termination
No parallel DQS termination is required with ODT of SDRAMs used.
Routing Guideline 1
Route all data signals and associated strobes on same layer.
Routing Guideline 2
Minimize layer changes especially on clock and DQS signals. (two vias or less)
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