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Intel

80303 and 80302 I/O Processors

Specification Update

Documentation Changes

Table 24-4 on pg 24-8 is incorrect

Problem:

Table 24-4 on pg 24-8 is incorrect.

Workaround:

Replace Table 24-4 with the following table:

Table 24-4.

Intel

80303 I/O Processor Boundary Scan Register Bit Order (Sheet 1 of 10)

Cell Type

Name

Function Safe bit

Control Signal

Disable Value

Disable Result

(CBSC_1,

scl,

bidir,

Z)," &

(BC_1,

control,

1)," &

(CBSC_1,

sda,

bidir,

Z)," &

(BC_1,

control,

1)," &

(BC_1,

rale,

output3,

111,

Z)," &

(BC_1,

roez,

output3,

111,

Z)," &

(CBSC_1,

rad(15),

bidir,

Z)," &

(BC_1,

control,

0)," &

(BC_1,

rcez(1),

output3,

Z)," &

(BC_1,

control,

0)," &

"10

(BC_1,

rcez(0),

output3,

11,

Z)," &

"11

(BC_1,

control,

0)," &

"12

(CBSC_1,

rad(6),

bidir,

28,

Z)," &

"13

(BC_1,

rwez,

output3,

111,

Z)," &

"14

(CBSC_1,

rad(9),

bidir,

18,

Z)," &

"15

(CBSC_1,

rad(10),

bidir,

16,

Z)," &

"16

(BC_1,

control,

0)," &

"17

(CBSC_1,

rad(11),

bidir,

18,

Z)," &

"18

(BC_1,

control,

0)," &

"19

(CBSC_1,

rad(13),

bidir,

20,

Z)," &

"20

(BC_1,

control,

0)," &

"21

(CBSC_1,

rad(12),

bidir,

22,

Z)," &

"22

(BC_1,

control,

0)," &

"23

(CBSC_1,

rad(8),

bidir,

28,

Z)," &

"24

(CBSC_1,

rad(14),

bidir,

25,

Z)," &

"25

(BC_1,

control,

0)," &

"26

(CBSC_1,

rad(2),

bidir,

28,

Z)," &

"27

(CBSC_1,

rad(1),

bidir,

28,

Z)," &

"28

(BC_1,

control,

1)," &

"29

(CBSC_1,

rad(16),

bidir,

30,

Z)," &

"30

(BC_1,

control,

0)," &

"31

(CBSC_1,

rad(0),

bidir,

28,

Z)," &

"32

(CBSC_1,

rad(5),

bidir,

28,

Z)," &

"33

(CBSC_1,

rad(4),

bidir,

28,

Z)," &

"34

(CBSC_1,

rad(3),

bidir,

28,

Z)," &

"35

(BC_4,

nc1,

input,

X)," &

"36

(CBSC_1,

rad(7),

bidir,

28,

Z)," &

"37

(CBSC_1,

GPIO(0),

bidir,

38,

Z)," &

"38

(BC_1,

control,

1)," &

"39

(CBSC_1,

GPIO(1),

bidir,

40,

Z)," &

"40

(BC_1,

control,

1)," &

"41

(CBSC_1,

GPIO(2),

bidir,

42,

Z)," &

Содержание 80302

Страница 1: ...The Intel 80303 and Intel 80302 I O Processors processor may contain design defects or errors known as errata Characterized errata that may cause the product s behavior to deviate from pubished specif...

Страница 2: ...are subject to change Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an ordering num...

Страница 3: ...O Processors Specification Update 3 Contents Revision History 5 Preface 7 Summary Table of Changes 8 Identification Information 14 Errata 16 Specification Changes 23 Specification Clarifications 25 D...

Страница 4: ...4 Intel 80303 and 80302 I O Processors Specification Update This Page Intentionally Left Blank...

Страница 5: ...ument Changes 25 through 29 Revised Device ID Registers A 2 Revision ID Registers data Added Note to Device ID Registers 04 02 01 005 Added Specification Clarification 3 03 22 01 004 Added Errata 1 Ad...

Страница 6: ...hanges are modifications to the current published specifications These changes will be incorporated in any new release of the specification Specification Clarifications describe a specification in gre...

Страница 7: ...s Used in Summary Table Stepping X Errata exists in the stepping indicated Specification Change or Clarification that applies to this stepping No mark or Blank box This erratum is fixed in listed step...

Страница 8: ...Page Status Specification Changes A 2 1 X 14 Doc Summary of the Intel 80302 I O Processor Specification Clarifications No Steppings Page Status Specification Clarifications A 0 A 1 A 2 1 X X X 15 Doc...

Страница 9: ...oc Table 14 46 on page 14 109 has missing data 17 272353 001 34 Doc Section 13 2 4 3 on page 13 30 has incorrect data 18 272353 001 34 Doc Figure 15 3 on page 15 7 has missing text 19 272353 001 34 Do...

Страница 10: ...d testing GC80303 A 0 Q196 3 3 100 Samples limited testing GC80303 A 1 Q189 3 3 100 Samples limited testing GC80303 A 1 SL4Q4 3 3 100 Production GC80303 A 2 SL57T 3 3 100 Production Yield improvement...

Страница 11: ...DR 0x1008 Address Translation Unit Revision ID Register ATURID 0x1208 Intel i960 Core Processor Device ID DEVICEID 0xFF00 8710 80303 A 0 08879013 0x00 0x00 00823013 80303 A 1 18879013 0x01 0x01 008230...

Страница 12: ...with some specific instruction cache conditions can scoreboard a local or global register indefinitely When this happens processing can stall at the next access to that register awaiting a scoreboard...

Страница 13: ...n as normal unless they access the scoreboarded register and also stall Not all 80303 processors have been observed to exhibit this errata Implication Systems containing this instruction sequence may...

Страница 14: ...applications that use the I2 C unit the I2 C clock is generated from the internal bus clock so the ICCR I2 C Clock Count Register needs to be properly adjusted The Device ID Register DIDR 1002H in the...

Страница 15: ...o initiate configuration cycles to PCI target devices On page 15 57 Table 15 26 in the Intel 80303 I O Processor Developer s Manual these registers are stated as Not Available in PCI Configuration Spa...

Страница 16: ...Documentation Changes 32 and 33 for corrections to the datasheet and manual 7 PCI Local Bus Specification Revision 2 3 Compliancy Problem The Intel 80303 I O processor 80303 was designed to be compli...

Страница 17: ...3 on pg 9 9 did not print correctly Problem Figure 9 3 on pg 9 9 did not print correctly Workaround Replace Figure 9 3 with the following A6406 01 31 0 Fault Data Override Fault Data Fault Data Resum...

Страница 18: ...orkaround Replace Figure 13 22 with the following Affected Docs Intel 80303 I O Processor Developer s Manual 4 Figure 13 18 pg 13 35 Problem Replace Figure 13 18 with the following Affected Docs Intel...

Страница 19: ...he following Affected Docs Intel 80303 I O Processor Developer s Manual A6490 01 PCI Master Slave IB Master Slave P_ORQ 16 Bytes P_IWQ 256 Bytes P_OWQ 16 Bytes P_OTQ P_IWQAD P_IDWQ 8 Bytes P_ITQ1 P_IT...

Страница 20: ...found in Appendix C Peripheral Memory Mapped Registers There are four control and status registers for the PCI And Peripheral Interrupt Controller GPIO Output Enable Register GPIO Input Data Register...

Страница 21: ...t3 X 11 0 Z 11 BC_1 control 0 12 CBSC_1 rad 6 bidir X 28 1 Z 13 BC_1 rwez output3 X 111 1 Z 14 CBSC_1 rad 9 bidir X 18 0 Z 15 CBSC_1 rad 10 bidir X 16 0 Z 16 BC_1 control 0 17 CBSC_1 rad 11 bidir X 18...

Страница 22: ...ogic1 input X 63 BC_1 failz output3 X 110 1 Z 64 BC_4 nmiz input X 65 BC_1 control 1 66 BC_4 nc3 input X 67 BC_4 nc4 input X 68 BC_4 nc5 input X 69 BC_4 nc6 input X 70 BC_4 nc7 input X 71 BC_4 nc8 inp...

Страница 23: ...2 CBSC_1 dq 5 bidir X 202 0 Z 113 CBSC_1 dq 6 bidir X 202 0 Z 114 CBSC_1 dq 8 bidir X 202 0 Z 115 CBSC_1 dq 42 bidir X 204 0 Z 116 CBSC_1 dq 7 bidir X 202 0 Z 117 CBSC_1 dq 45 bidir X 204 0 Z 118 CBSC...

Страница 24: ...Z 158 BC_1 sdqm 3 output3 X 205 1 Z 159 BC_1 scke 0 output3 X 205 1 Z 160 BC_1 sdqm 6 output3 X 205 1 Z 161 CBSC_1 scb 2 bidir X 200 0 Z 162 CBSC_1 scb 3 bidir X 200 0 Z 163 BC_1 sdqm 7 output3 X 205...

Страница 25: ...dir X 325 0 Z 207 CBSC_1 s_ad 34 bidir X 325 0 Z 208 CBSC_1 s_ad 42 bidir X 325 0 Z 209 CBSC_1 s_ad 36 bidir X 325 0 Z 210 CBSC_1 s_ad 33 bidir X 325 0 Z 211 CBSC_1 s_ad 32 bidir X 325 0 Z 212 CBSC_1...

Страница 26: ..._1 s_ad 3 bidir X 329 0 Z 252 CBSC_1 s_ad 4 bidir X 329 0 Z 253 CBSC_1 s_ad 7 bidir X 329 0 Z 254 CBSC_1 s_ad 1 bidir X 329 0 Z 255 CBSC_1 s_cbez 0 bidir X 330 0 Z 256 CBSC_1 s_ad 5 bidir X 329 0 Z 25...

Страница 27: ...6 0 Z 298 CBSC_1 s_ad 27 bidir X 326 0 Z 299 CBSC_1 s_ad 29 bidir X 326 0 Z 300 CBSC_1 s_ad 31 bidir X 326 0 Z 301 BC_1 s_rstz output3 X 333 1 Z 302 BC_1 s_holdaz output3 X 321 0 Z 303 BC_4 s_holdz in...

Страница 28: ...utput3 X 349 0 Z 349 BC_1 control 0 350 CBSC_1 p_ad 31 bidir X 455 0 Z 351 BC_1 p_reqz output3 X 352 0 Z 352 BC_1 control 0 353 CBSC_1 p_ad 26 bidir X 455 0 Z 354 CBSC_1 p_ad 29 bidir X 455 0 Z 355 CB...

Страница 29: ...0 bidir X 452 0 Z 393 BC_4 p_m66en input X 394 CBSC_1 p_ad 6 bidir X 452 0 Z 395 CBSC_1 p_ad 4 bidir X 451 0 Z 396 CBSC_1 p_ad 8 bidir X 451 0 Z 397 CBSC_1 p_ad 7 bidir X 451 0 Z 398 BC_4 p_clk input...

Страница 30: ...ir X 447 0 Z 432 CBSC_1 p_ad 44 bidir X 447 0 Z 433 CBSC_1 p_ad 45 bidir X 447 0 Z 434 CBSC_1 p_ad 43 bidir X 447 0 Z 435 CBSC_1 p_ad 41 bidir X 447 0 Z 436 CBSC_1 p_ad 42 bidir X 447 0 Z 437 CBSC_1 p...

Страница 31: ...owing It supports clock frequencies up to a maximum of 100 MHz Affected Docs Intel 80303 I O Processor Developer s Manual Figure 25 1 Intel 80303 I O Processor Clocking Regions Diagram A8053 01 P_CLK...

Страница 32: ...nput Clock Region Clock Buffered PLL P_M66EN S_M66EN P_CLK 33 MHz Region 1 1x P_CLK Buffered 0 0 Region 2 3x P_CLK PLL Region 3 3x P_CLK PLL Region 4 1x P_CLK Buffered P_CLK 66 MHz Region 1 1x P_CLK B...

Страница 33: ...al bus interface The internal bus on the 80303 I O processor is 100 MHz Workaround Change the last bullet to the following 64 bit 66MHz PCI and 64 bit 100 MHz internal bus interface Affected Docs Inte...

Страница 34: ...er It should be Base_Register Value of Limit_Register Workaround Replace Figure 15 3 with the following Affected Docs Intel 80303 I O Processor Developer s Manual 19 Section 15 7 39 on page 15 100 has...

Страница 35: ...m 32 to 528 Mbytes It should be 512 Mbytes not 528 Mbytes Workaround Change this sentence to the following The MCU supports an ECC only memory subsystem ranging from 32 to 512 Mbytes Affected Docs Int...

Страница 36: ...and add the adjacent paragraph with new Figure 13 16 Figure 13 16 shows how the data flows through the ECC hardware for a read transaction Affected Docs Intel 80303 I O Processor Developer s Manual T...

Страница 37: ...M RN I O processor Since the customer cannot see the internal bus whatever is on it is not useful and is only confusing Therefore this section has been removed Affected Docs Intel 80303 I O Processor...

Страница 38: ...1 steppings of the 80303 See Specification Clarification 6 for A 2 stepping functionality Affected Docs Intel 80303 I O Processor Datasheet 33 Section 17 5 1 on page 17 12 is only correct for A 0 and...

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