IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -74
Q206: ENVY24MT (PCI Multi-channel Audio Controller)
TX-NR906/NA906
TERMINAL DESCRIPTION(1/2)
I - Input Signal
O - Output Signal
B - Bidirectional Signal
OD - Open Drain
A - Analog Signal
PU - Pull-up. 50 kohm nominal
PCI BUS INTERFACE
Symbol
Type
Description
AD[31:0]
B
Multiplexed PCI Address / Data Bus.
CBE#[3:0]
B
Bus Command / Byte Lane Enable.
These signals are bus commands during the address phase
and byte lane enable during the data phase. These signals are output during a bus master cycle.
PCICLK
I
PCI Bus Clock.
DEVSEL#
B
Device Select.
The VT1720T drives this signal active when it decodes its address as the current target
of the current acces.
FRAME#
B
PCI Cycle Frame.
When asserted by the bus mster, this signal indicates the beginning of a bus
transaction.During the final data phase of a bus transaction it is deasserted.
GNT#
I
PCI Bus Grant.
When active it indicates bus master is granted to the VT1720T.
IDSEL
I
Initialization Device Select.
This is the chip select during the PCI configuration register accesses
INTA#
OD
PCI Interrupt Request.
IRDY#
B
Initiator Ready.
PAR
B
Parity.
REQ#
O
Bus Master Control Request.
RST#
I
System Reset.
All VT1720T registers and state machines are at default when this signal is asserted.
STOP#
B
Target Disconnect.
TRDY#
B
Target Ready.
I
²
C PORT
Serial Data.
Serial Bit Shift Clock.
MPU-401 UART
MPU-401 Transmit Data.
MPU-401 Receive Data.
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