DTR-6.4
CLR
L
H
L
H
H
H
PR
H
L
L
H
H
H
D
X
X
X
L
H
X
CK
X
X
X
Q
L
H
H
L
H
Qn
Q
H
L
H
H
L
Qn
CLEAR
PRESET
NO CHANGE
INPUTS
OUTPUTS
FUNCTION
X: Don't care
TC74VHC74FT(Dual D-FF with preset and clear)
1
2
3
4
5
6
7
1CLR
1D
1CK
1PR
1Q
1Q
GND
14
13
12
11
10
9
8
Vcc
2CLR
2D
2CK
2PR
2Q
2Q
CK D
Q Q
CK D
Q Q
1A
1B
1Y
2A
2B
2Y
GND
Vcc
4B
4A
4Y
3B
3A
3Y
1
2
3
4
5
6
7
14
13
12
11
10
9
8
TC74VHCT00AFT(2-input NAND gate)
A
L
L
H
H
B
L
H
L
H
Y
H
H
H
L
IC BLOCK DIAGRAMS AND DESCRIPTIONS
1A
1Y
2A
2Y
3A
3Y
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Vcc
6A
6Y
5A
5Y
4A
4Y
(TOP VIEW)
A
L
H
Y
H
L
Truth table
74HC04F/TC74VHCU04FT(Hex Inverters)
1A
3Y
2A
GND
1
2
3
4
8
7
6
5
Vcc
1Y
3A
2Y
Truth Table
A
Y
L
H
H
L
TC7WU04F(3 Inverters)
