Integra DPS-7.3, Руководство по обслуживанию

Страница: 41 / 48

DPS-7.3
MICROPROCESSOR BLOCK DIAGRAM / TERMINAL DESCRIPTION
Q701 : (uPD780232GC)
No. PIN NAME I/O
1 VDD1 VDD1 Power supply pin. +5V
2 VSS1 VSS1 Ground pin without analog section
3 X1 X1 Main clock input pin (5MHz)
4 X2 X2
5 IC IC I
6 RESET RESET I
7 P27/SCK1 XSCK O
8 P26/SI1 SI I
9 P25/SO1 SO O
10 P24/BUSY XRDY O
11 P23 PON O
12 P22 SYSRESET O
13 P21/SO3 DISPLAY_MODE I
14 P20/SCK3 LT1 I
15 P00/INTP0 REMO I
16 P01/INTP1 IRIN I
17 P02/TI VCOFF O
18 AVSS AVSS
19 ANI3 INIT1 I
20 ANI2 ANI2 I
21 ANI1 ANI1 I
22 ANI0 ANI0 I
23 VSS0 VSS0
24 AVDD AVDD
25 VDD0 VDD0
26 P64/FIP52 SYSIN I
27 P63/FIP51 SYSOUT O
28 P62/FIP50 R232REQ I
29 P61/FIP49 R232BUSY I
30 P60/FIP48 R232SI I
31 P57/FIP47 R232SCK O
32 P56/FIP46 R232SO O
33 P55/FIP45 TEST O
34 P54/FIP44 R232RES O
35 P53/FIP43 FLON_OFF O
36 P52/FIP42 MSO_2 I
37 P51/FIP41 MSO_1 I
38 P50/FIP40 MSO_0 I
39 P47/FIP39 STBYLED O
40 P46/FIP38 VCOFFLED O
41 P45/FIP37 SACD192LED O
42 P44/FIP36 DVD96LED O
43 P43/FIP35 PLYLED O
44 P42/FIP34 STPLED O
45 P41/FIP33 OPCLLED O
46 P40/FIP32 CDPORT O
47 P37/FIP31 PAUSELED O
48 P36/FIP30 CD48LED O
49 P35/FIP29 POWERLED O
50 P34/FIP28 P15 O
51 P33/FIP27 P14 O
52 P32/FIP26 P13 O
53 P31/FIP25 P12 O
54 P30/FIP24 P11 O
55 FIP23 P10 O
56 FIP22 P9 O
57 FIP21 P8 O
58 FIP20 P7 O
59 VDD2 VDD2
60 VLOAD VLOAD
61 FIP19 P6 O
62 FIP18 P5 O
63 FIP17 P4 O
64 FIP16 P3 O
65 FIP15 P2 O
66 FIP14 P1 O
67 FIP13 14G O
68 FIP12 13G O
69 FIP11 12G O
70 FIP10 11G O
71 FIP9 10G O
72 FIP8 9G O
73 FIP7 8G O
74 FIP6 7G O
75 FIP5 6G O
76 FIP4 5G O
77 FIP3 4G O
78 FIP2 3G O
79 FIP1 2G O
80 FIP0 1G O
Connect to ground pin
Reset pin of microprocessor
Clock output pin for writing of flash ROM
Data input pin for writing flash ROM
Data output pin for writing flash ROM
XRDY output pin
Power ON control signal output pin. (ON : "H")
Reset control signal pin
Select the display mode for exhibition. (Exhibition mode : "L")
LT1 data input pin
Remote control signal input pin.
Not used.
Video circuit off control output pin. (L : mute)
Ground pin for A/D converter.
Initializing input pin at analog input.
Analog signal input pin of A/D converter.
Analog signal input pin of A/D converter.
Analog signal input pin of A/D converter.
Ground pin.
Power supply pin of A/D converter. (Same as VDD1)
Power supply pin. +5V
System buss input pin.
System buss output pin.
REQ signal input pin from microprocessor of RS-232C driver.
BUSY signal input pin from microprocessor of RS-232C driver.
SI signal input pin from microprocessor of RS-232C driver.
CK signal output pin from microprocessor of RS-232C driver.
SO signal output pin from microprocessor of RS-232C driver.
To connect to ground pin.
Open pin.
FL filament on/off control output pin.
Model select input pin 2.
Model select input pin 1.
Model select input pin 0.
Standby LED control output pin.
Video circuit off control signal output pin.
Sampling rate 192kHz signal control output pin.
Sampling rate 96kHz signal control output pin.
Play signal control output pin.
Stop signal control output pin.
Open/ close signal control output pin.
Not used.
Pause signal control output pin.
Sampling rate 48kHz signal control output pin.
Power LED control output pin.
FL segment (P15) control output pin.
FL segment (P14) control output pin.
FL segment (P13) control output pin.
FL segment (P12) control output pin.
FL segment (P11) control output pin.
FL segment (P10) control output pin.
FL segment (P9) control output pin.
FL segment (P8) control output pin.
FL segment (P7) control output pin.
Power supply pin. +5V
FIP control pin to connect pull down resistor.
FL segment (P6) control output pin.
FL segment (P5) control output pin.
FL segment (P4) control output pin.
FL segment (P3) control output pin.
FL segment (P2) control output pin.
FL segment (P1) control output pin.
FL grid (G14) control output pin.
FL grid (G13) control output pin.
FL grid (G12) control output pin.
FL grid (G11) control output pin.
FL grid (G10) control output pin.
FL grid (G9) control output pin.
FL grid (G8) control output pin.
FL grid (G7) control output pin.
FL grid (G6) control output pin.
FL grid (G5) control output pin.
FL grid (G4) control output pin.
FL grid (G3) control output pin.
FL grid (G2) control output pin.
FL grid (G1) control output pin.
I
I
SIGNAL NAME DESCRIPTION
41/48
www.denom.com