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Inrevium VIRTEX-5 TB-5V-LX110/220/330-DDR2, Руководство пользователя по оборудованию

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Inrevium VIRTEX-5 TB-5V-LX110/220/330-DDR2 Скачать руководство пользователя страница 21

 

 

Sep 

4, 2007 (Rev 2.1s)                                           

  21/26

 

TB-5V-LX110/220/330-DDR2Hardware User Guide Rev2.1s 

VBATT_0 Level Setting 

Virtex-5  has  the  function  of  configuration  encryption.  If  encryption  is  used,  it  needs  to  provide  a 
power supply to VBATT.   
It  is  possible  to  change  the  power  supply  of  VBATT_0  (R29)  of  FPGA  to  ‘H’  (3.3V)  or  ‘L’  (GND) 
using JP4. 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Figure.32 JP4 setting for VBATT_0 Level Selection 

 

Others 

There are ten of GND test points. It is useful to use oscilloscope and so on. (TP2 ~ TP11) 
 

 

 
 
 
 

Figure.33 GND Test Point 

 

VBATT_0 “L“ 

VBATT_0 “H“ 

Содержание VIRTEX-5 TB-5V-LX110/220/330-DDR2

Страница 1: ...ku Yokohama City Kanagawa Japan 224 0045 E mail x2bdg teldevice co jp http www inrevium jp TB 5V LX110 220 330 DDR2 VIRTEX 5 Multi Application Platform Board TB 5V LX110 220 330 DDR2 Hardware User Gu...

Страница 2: ...r for I O connectors 9 Power Voltage Selector for LVDS connectors 10 Power Voltage Selector for I O pin header connectors 11 Oscillator 12 PLLIC ICS8430 61 Setting 13 User DIP Switch 14 Pushbutton Swi...

Страница 3: ...yo Electron Device Limited shall not be liable for any consequences or damages resulting from the uses that are not described in this document No one is permitted to reproduce quote or distribute this...

Страница 4: ...Module is not included Configuration Tokyo Electron Device TE7725PF is a FPGA configuration control LSI which is developed by Tokyo Electron Device TE7725PF enables to configure Xilinx FPGA with a ge...

Страница 5: ...760pin Data DQS ADR CLK Command Data DQS ADR CLK Command General I O 100pin 4 LTM4600 LTC3728L LTC3413 1 0V 1 8V 3 3V 0 9V Power Connector Clock Synth ICS8430I 61 133to400MHz OSC 16MHz LAN9118 RJ45 LV...

Страница 6: ...PC4 Connect P 56 JTAG Pin Header P 56 Option I O Power Setting P 9 Config Mode Setting P 68 OSC Socket P 13 Program LED P 51 VBATT_0 Level Setting P 54 Flash Memory Area Setting SW P 52 6 External Vi...

Страница 7: ...5V Vref Vin FPGA Core FPGA I O Bank 3 3V Device FPGA VCCAUX I O Bank 2 5V Device FPGA I O Bank DDR2 SDRAM FPGA Vref DDR2 Vref VTT 8 Board Components Power Connector and Power Module Single 12V power...

Страница 8: ...LED19 indicate that the power supply is running normally Ensure that all Leeds are turned on otherwise something is wrong with the board Switch off the power supply since there may be a short circuit...

Страница 9: ...per to the desired power voltage 2 5V or 3 3V in accordance with interface level JP1 is the jumper for Configuration Mode P 68 Figure 6 Jumper setting for power of Option I O connector Set power selec...

Страница 10: ...ctors It is possible to select 2 5V or 3 3V for VCCO power voltage of LVDS connectors Bank20 Bank24 Connected to LVDS I O connector Set jumper to the desired power voltage 2 5V or 3 3V in accordance w...

Страница 11: ...elect 2 5V or 3 3V for VCCO power voltage of LVDS connectors Bank19 Connected to Pin header I O connector User DIP switch User Push switch Set jumper to the desired power voltage 2 5V or 3 3V in accor...

Страница 12: ...set the 16MHz oscillator that comes with the board to a correct pin position of the oscillator socket X1 that is connected to the PLLIC If an oscillator other than that provided with the board is use...

Страница 13: ...N 2 setting generates 125MHz clock Fout 16 6x250 2 125MHz Table 3 ICS8430 61 Setting Note Value 1 or 0 of the setting M0 M6 N0 and N2of DIP switches When the setting of DIP switches are ON each value...

Страница 14: ...3V according to Pin Header Figure 11 DIP Switch Setting Pushbutton Switch Six pushbutton switches are connected to the I O of FPGA While each switch is pushed FPGA I O is set to High The signal level...

Страница 15: ...ith connecting with PC Then the cable is used Cross Cable that is available commercially Figure 14 RS 232C Block Diagram Figure 15 RS 232C RS232C Driver can set On Off by Jumper SW Short between 2 3 o...

Страница 16: ...2 1s 16 26 TB 5V LX110 220 330 DDR2Hardware User Guide Rev2 1s DDR2 SDRAM SO DIMM Socket DDR2 SO DIMM socket is mounted on this board It is possible to use up to 2GB DDR2 SO DIMM Figure 17 DDR2 SDRAM...

Страница 17: ...CK CK DDR2SDRAM 512 M IC31 DQ 16 DQS 8 DQS 8 DM 2 CS DDR2 SDRAM Memory Component Three pieces of DDR2 SDRAM component 512Mb is used on this board Two Configurations The connection between FPGA and me...

Страница 18: ...select 2 5V or 3 3V it is possible to select another I O standard not only LVDS Figure 21 LVDS I O Connector High Speed Extension I O Connector For realizing variable interface there are four connecto...

Страница 19: ...al level to 2 5 or 3 3V according to connected interface Figure 23 Multi Purpose I O Pin Header Soft Touch Connector Soft Touch Connector produced by Agilent Technology is mounted between FPGA and DDR...

Страница 20: ...0 64Mbit Flash 2 4Region 16Mbit Top Sector 0 0 1 1 0 64Mbit Flash 1 4Region 16Mbit Top Sector 1 0 1 1 0 64Mbit Flash 3 4 4 4Region 32Mbit Top Sector 0 1 1 1 0 64Mbit Flash 1 4 2 4Region 32Mbit Top Se...

Страница 21: ...ion If encryption is used it needs to provide a power supply to VBATT It is possible to change the power supply of VBATT_0 R29 of FPGA to H 3 3V or L GND using JP4 Figure 32 JP4 setting for VBATT_0 Le...

Страница 22: ...flash memory using a TD LB2CABLE attached in this board or Parallel Cable III or IV First programmming a configuration file MCS to flash memory using each download cable Then configuration of FPGA is...

Страница 23: ...X110 220 330 DDR2Hardware User Guide Rev2 1s FPGA Virtex 5 CN1 PC4 CN2PC3 JTAG Figure 35 JTAG Connector Or it is possible to program to FPGA directly via CN1 or CN2 Figure 36 Configuration Structure 2...

Страница 24: ...e following 1 4 are descriptions of FPGA configuration 1 Set JP1 BPI UP mode Note JP2 6 7 8 9 10 are jumpers for power supply setting of I O Banks Page 9 Figure 59 BPI UP Mode Setting 2 Set SW3 as Fig...

Страница 25: ...30 DDR2Hardware User Guide Rev2 1s 3 If FPGA configuration is completed LED2 Green will light Configuration completed Figure 61 DONE LED 4 If Reconfiguration bottom SW2 is pushed start a reconfigurati...

Страница 26: ...s document is subject to change without prior notice In no event shall Tokyo Electron Device Limited be liable for any extraordinary losses or incidental damages arising from the typographical error o...

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