TB-FMCL-MIPI Hardware User Manual
16
Rev.3.01
data and one lane is assigned as clock. The HS mode data lanes operate in DDR mode with respect to
the clock, with one data bit transferred per clock transition. The Receiver (CSI-2) converts five low-swing,
high-
speed differential signals (SLVS per Meticom’s terminology) to five LVDS links (4-data, 1-clock) sent
to the FMC LPC connector. The Transmitter (DSI) converts five LVDS links from the FMC LPC connector
to five SLVS links. Refer to the respective device datasheet for more details regarding electrical
characteristics and performance.
8.3. LP Mode Interface
Each PHY device also presents an alternate set of differential IOs, termed the CMOS LP(0-4). These
pins operate at LVCMOS level determined by VADJ, at up to 10Mb/s, and are active during Low-Power
(LP) mode transactions defined in the MIPI Specification. Low-power mode additionally features Bus
Turn Around (BTA) where the data direction on one of the CMOS LP links (Lane 0) is reversed to provide
host system read/write access to status and control registers from either a DSI (display) or CSI-2
(camera) MIPI peripheral. This facility supports minimized peripheral connectivity where additional
GPIOs, I2C or other side-band control links are absent.
8.4. PHY Control
Each PHY device presents a group of four control inputs to the host which govern the operation of the
MIPI link. Two pins, called GPIO-1 and GPIO-2, set the operating state of the PHY. Another input pin,
BTA, enables the Bus Turn Around (in LP) mode and is used for host access to status and control
registers within the peripheral device. The final input pin, called PINSWAP, is a three-mode input which
controls the differential polarity of all five MIPI lanes simultaneously. The following table outlines the
operating modes of the PHY device as selected by the input settings:
Table 8-1 MIPI PHY Mode Settings
Input Pins
Mode
GPIO-1 GPIO-0 BTA
PINSWAP
0
0
X
X
IC Power Down
0
1
X
X
SLVS-LVDS conversion unconditionally active
1
0
0
X
MIPI D-PHY mode, BTA not Active during LP
1
0
1
X
MIPI D-PHY mode, BTA Active on PHY channel E during LP
0
1
0
X
*MIPI D-PHY mode, BTA not Active during LP
0
1
1
X
*MIPI D-PHY mode, BTA Active on PHY channel A during LP
X
X
X
0
No HS Pin polarity Swaps
X
X
0
1
HS Pin polarity swap each lane at the MIPI port
X
X
1
1
No HS Pin polarity Swaps
X
X
X
**Floating
HS Pin polarity swap each lane at the LVDS HS port
* BTA on Channel A / MIPI lane 4 is not supported on the TB-FMCL-MIPI card. These settings should not
be used.
** This option is available by removing the appropriate shorting jumper from J3: pins 1-2 for CSI, pins 3-4
for DSI. Removed jumpers may be parked on unconnected pins 5-6 and 7-8. The user must ensure
that the jumpers are installed across pins 1-2 and 3-4 to select No Pin Swap mode.
