TB-FMCH-HDMI4K Hardware User Manual
25
Rev.2.04
also be used to synchronously generate the video clocks. The CKIN2 input is not used. Figure 10-1
shows how the Si5324 is connected to the main board and how the extender FMC Si5324 is connected.
Please refer to the Si5324 data sheet for how to set the registers to produce the desired clocks.
Figure 10-1 Si5324A Clock Generator
Note:
Due to I/O limitations on the J3 Main Board FMC connector, the stacked FMC’s Si5324 clock
generator only provides EX_CLK_LVDS_P/N to the J8 connector.
10.2. HDMI Source Clock
The SN65DP159 drives the HDMI source TMDS differential clock using the clock from its IN_CLKp/n
input. A Texas Instruments TS3USB221 1:2 multiplexer is used to feed IN_CLKp/n. This allows a choice
CKOUT1-
CKOUT2-
XA
XB
114.285 MHz
Crystal
CKIN1+
CKIN1-
CKIN2+
CKIN2-
not used
SN74AVC4T245
Voltage Translator
PCA9517 I2C Bus
Repeater
SCL
SDA_SDO
INT_C1B
LOL
RSTn
RATE0
RATE1
CS_CA
A0
A1
A2_SSn
CMODE
pulled low
B20
B21
H4
H5
GBTCLK1_M2C_P
GBTCLK1_M2C_N
CLK0_M2C_P
CLK0_M2C_N
H7
H8
LA02_P
LA02_N
G6
G7
LA00_CC_P
LA00_CC_N
C10
C11
LA06_P
LA06_N
SN74AVC4T245
Voltage Translator
C14 LA10_P
not connected
D20
D21
LA17_CC_P
LA17_CC_N
G6
G7
LA00_CC_P
LA00_CC_N
EX_CLKIN_LVDS_P
EX_CLKIN_LVDS_N
H4
H5
CLK0_M2C_P
CLK0_M2C_N
CLK1_M2C_P
G2
G3
CLK1_M2C_N
EX_CLK_LVDS_P
EX_CLK_LVDS_N
CLKIN_LVDS_P
CLKIN_LVDS_N
CLK_LVDS_P
CLK_LVDS_N
CLK_MGT_REFCLK_P
CLK_MGT_REFCLK_N
H7
H8
LA02_P
LA02_N
C10
C11
LA06_P
LA06_N
C14
LA10_P
EX_CLKIN_VALID
EX_PLL_LOL
CLK_EX_I2C_CTL_SCL
EX_I2C_CTL_SDA_OD
EX_REF_CLK_RST_N
G12
G13
LA08_P
LA08_N
D8
D9
LA01_CC_P
LA01_CC_N
D11 LA05_P
Si5324
J8 FMC
Connector
for Extender
Card
J3 FMC
Connector for
Main Board
