TB-FMCH-HDMI4K Hardware User Manual
8
Rev.2.04
1. Related Documents and Accessories
All documents relating to this board can be downloaded from the TED Support Web at address
https://www.teldevice.co.jp/spweb/c0208s
Table 1-1 Accessories
Description
Manufacturer
Quantity
Spacer, 10mm, M2.6
Hirosugi
2
Spacer, 10mm w/ screw, M2.6
Hirosugi
4
Spacer, 25mm, M2.6
Hirosugi
2
Screw, 6mm, M2.6 w/ washers
Hirosugi
6
2. Overview
The TB-FMCH-HDMI4K is functionally divided into a source circuit and a sink circuit. Each side is
designed to be compatible with the HDMI 2.0 specification, with an individual TMDS channel
throughput of up to 6 Gbps thus enabling support of 4K resolution at 60fps. The source circuit is
based on the Texas Instruments SN65DP159 D++ to TMDS Retimer.
The TB-FMCH-HDMI4K has demonstrated operation up to 4096x2160p 60Hz.
For the latest support resolution, please refer to the following Xilinx HDMI IP web page.
http://www.xilinx.com/products/intellectual-property/hdmi.html
The TB-FMCH-HDMI4K utilizes HDMI Type-A receptacles and Samtec’s FMC HPC connector for
connection to a platform board having a High-Pin Count (HPC) connector.
Physically, this FMC is a single width air-cooled card that is compatible with the ANSI/VITA 57.1
FPGA Mezzanine Card (FMC) Standard.
The Display Data Channel (DDC) and Consumer Electronics Control (CEC) are supported. An I2C
controlled clock multiplier/generator is included to produce a reference frequency of up to 346MHz.
A second FMC HPC connector allows a second TB-FMCH-HDMI4K to be stacked to expand to two
source and two sink circuits.
Note:
Only stack FMCs that are identical (i.e. same part number and same revision). Do not attempt to
stack different FMCs. Stacking FMCs of different types or revisions could cause damage.
Note:
Due to I/O constraints on the FMC connector there are restrictions on the capabilities of the
stacked FMC:
a. The HDMI sink clock on the second extender FMC is not connected to the J3 FMC
main board connector. This practically limits the sink operation of the stacked FMC to
the same sink clock frequency as the primary FMC and generally the same traceable
source to avoid clock slipping.
b. Due to I/O limitations on the J3 Main Board FMC connector, the stacked FMC’s
Si5324A clock generator only provides EX_CLK_LVDS_P/N to the J8 connector. This
