Application Note
11 of 33
002-33887 Rev. *A
2022-05-25
Using the Watchdog Timer in XMC7000 family MCUs
Basic WDT
2.8
Clearing the basic WDT
Clearing the basic WDT is performed by setting the SERVICE[0] bit to ‘1’ in the SERVICE register. The firmware
must consider reading this bit until it is ‘0’ before writing ‘
1
’
to this bit.
Servicing of the basic WDT counter must be done regularly to ensure a stable software flow. Independent of the
software concept used, the runtime calculation of software components is crucial to define the limits of the
counter to be cleared. The window mode makes it even more complex because a minimum time period needs
to be determined before which the software is not expected to service the basic WDT. This minimum time
period can be, for example, the minimum execution time of a low-priority main function.
shows an example of when the watchdog counter can be cleared within a system with different tasks.
The calculation of each service moment must consider the following conditions:
1.
In the window mode, do not service the watchdog before the counter reaches the LOWER_LIMIT.
2.
Must service the watchdog counter before reaching the UPPER_LIMIT to avoid a reset event.
The following conditions are defined:
•
UPPER_LIMIT = 0x8000: Upper reset threshold is 1 second
•
LOWER_LIMIT = 0x1000: Minimum reset threshold is 125 ms
•
Task 1 duration: 100 ms
•
Task 2 duration: 300 ms
•
Task 3 duration: 200 ms
•
Task 4 duration: 150 ms
•
Task 5 duration: 200 ms
There are different sequences assumed with different timings:
•
Sequence 1: t
Task1
+ t
Task2
+ t
Task3
+ t
Task4
= 100 ms + 300 ms + 200 ms + 150 ms = 750 ms
•
Sequence 2: t
Task1
+ t
Task4
= 100 ms + 150 ms = 250 ms
•
Sequence 3: t
Task1
+ t
Task4
+ t
Task5
= 100 ms + 150 ms + 200 ms = 450 ms
In all cases, the following condition is met:
t
LOWER_LIMIT
< t
SEQUENCE
< t
UPPER_LIMIT
