User Manual
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V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Digital pulse width modulator
When a selected IO pin is mapped as an input, the sync function synchronizes to the rising edge of the provided
sync pulse. A 40 ns deglitcher is available on the sync input and it is enabled by setting register
sync_deglitch_en
to 1. It should be noted that enabling the deglitcher adds 40 ns of latency between the sync
pulse rising edge and the internal ramps.
The following points should be considered while using external synchronization:
•
To achieve initial synchronization lock to the incoming pulse, the input pulse frequency must be within 6.25
percent of the internal switching frequency that is programmed by PMBus command FREQUENCY_SWITCH.
•
Once initial lock is achieved, the sync function maintains lock over a range ±12.5 percent of the internal
switching frequency defined by PMBus command FREQUENCY_SWITCH.
•
In case the sync pulse frequency is outside the lock range or if no pulse is provided, the sync function reverts
to the frequency defined by FREQUENCY_SWITCH.
In order to monitor the sync function state in real time, the following read-only registers are available:
•
sync_in_range
•
sync_state
•
sync_in_period
•
sync_fly_period
provides a further description of these registers.
7.2
PWM pulse generator
The XDPP1100 contains 12 pulse generators, as was shown in
. There is one dedicated pulse generator
for each of the PWM outputs, PWM1 through PWM12. These pulse generators use the timing markers, t1 and t2,
from the ramp generator (discussed in
) to form a PWM pulse with coarse timing. The coarse
pulses are then fed to the interpolators where fine resolution timing information is used to create output pulses
with 78.125 ps resolution.
7.2.1
Pulse generator enable
Pulse generator, dedicated to certain PWM outputs, is enabled through a PMBus command FW_CONFIG_PWM.
This command defines which PWM outputs are allocated for a given system and loop in the following way:
•
PAGE0 command defines Loop 0
•
PAGE1 command defines Loop 1
The enable programming of each pulse generator depends on the actual system and the selected topology. The
command FW_CONFIG_PWM consists of two components defining which topology-specific FETs are assigned
to certain PWM outputs and thus a pulse generator. These two components are:
•
FW_CONFIG_PWM[11:0] = pwm_on_mask[11:0]
•
FW_CONFIG_PWM[27:16] = pwm_srfet_mask[11:0]
Both of these masks are used by the FW to enable the HW pulse generators. The first component
pwm_on_mask[11:0] defines which PWM outputs correspond to:
•
Primary-side FETs in an isolated topology
•
High-side FETs in a non-isolated buck topology
•
Power FETs in non-isolated boost or buck-boost topologies
The other mask pwm_srfet_mask[11:0] defines which PWM outputs correspond to:
•
Secondary-side FETs in an isolated topology
